Browsing by Author "Röser, Hans-Peter (Prof. Dr. rer. nat)"

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Development and implementation of the attitude control algorithms for the micro-satellite Flying Laptop
(2010) Yasir, Muhammad; Röser, Hans-Peter (Prof. Dr. rer. nat)
Growing interest in small satellites is propelled due to their cost effectiveness, less developmental time, evolveability, and performance. The fast growth is also connected with more challenges which are associated with small satellites. The Flying Laptop (FLP) is one such satellite which is under development at Institute of Space Systems (IRS) at University of Stuttgart. Beside from the scientific observation the FLP is demonstrator of several technology experiments including FPGA-based reconfigurable OBC with high computational capability. The ability to reconfigure enables the brain of the system to evolve and adapt to the changing requirements. Fast speed and true parallel computation are accompanying advantages of using FPGAs. The research presented in this thesis attempts to lay out essential foundations for developing, implementing and testing FPGA specific attitude control system. As a first step, the overall structure of ACS algorithms, its command hierarchy and its interaction with other sub-systems and system FDIR was developed in accordance with the requirements and constraints. The need of different operating modes suitable for different mission scenarios was identified at this stage. For scientific observation inertial pointing, nadir pointing, and target pointing modes are developed to achieve the pointing accuracy of 150 arc-sec. Apart from the payload image acquisition modes, several supporting modes of ACS operation are provided to facilitate its functioning in different set of conditions. A clear concept of safe mode with solar panels pointed toward the sun is established which will be used during any contingency situation. Detumble mode is provided to ease out the orbit insertion phase and Idle mode will be used for charging the on-board batteries by pointing the solar panels toward the sun. The sensor measurements will be obtained by using magnetometers, sun sensors, GPS, star tracker, and FOGs while the actuation will be provided by magnetic torquers and reactions wheels. In a developmental phase the implementation of the ACS algorithms is carried out in Matlab. The structure of ACS algorithms is developed in accordance with its implementation in FPGA as hardware. Embedded Matlab functions are used at this stage. Matlab is used at this stage to carry out the performance verification. In a next phase these algorithms are ported into FPGA using Handel-C developmental language which directly generates the hardware configuration of FPGA from a code similar to ANSI-C. A lot of effort was required at this stage to reduce the size of resulting hardware and to fit the ACS algorithms within the limited resources of FPGA. FPGA testing boards are used at this point to verify the results and performance. Another issue related with the implementation was to generate hardware libraries for fixed point computation of several mathematical functions. The testing of these algorithms is first carried out using Matlab/Simulink based simulation environment. For this the already present simulator was improved with the addition of several key blocks like the adding Earth's albedo effect , eclipse flag generator and simulation of power supply system. The communication interface between FPGA and simulation environment is realized by using RS-232 serial port. In a second step these algorithms are also tested with Model-based Development and Verification Environment. (MDVE) originally developed by EADS Astrium. The simulation environment based on MDVE was developed at Institute of Space Systems, University of Stuttgart. The communication between MDVE and FPGA is realized by using RS-422 to obtain the maximum baud rate. Generally, this work proves the possibility of using ACS algorithms as embedded hardware logic to meet the challenging requirements of accuracy. This work also presents different issues of developing, implementing and testing FPGA specific ACS algorithms. Different ways of optimizing the resulting hardware design are also discussed in this thesis which has not only proved their effectiveness in the ACS algorithms but these are also helpful in the development of other subsystems.