05 Fakultät Informatik, Elektrotechnik und Informationstechnik

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    A review of electromagnetic simulation and modelling approaches for the research on axial flux synchronous machines
    (2024) Schäfer, Adrian; Pecha, Urs; Parspour, Nejila; Kampker, Achim; Born, Henrik; Hartmann, Sebastian; Franke, Jörg; Baader, Marcel; Hahn, Roman
    Extensive electromagnetic (EMAG) studies are necessary to fully realize the potential of axial flux machines (AFMs). However, the disc-shaped air gap and the complex three-dimensional path of magnetic flux pose challenges in modelling AFMs compared to conventional radial flux machines. This study reviews current research on EMAG modelling and simulation of AFMs, highlighting the need for tools that address AFM-specific effects. Existing approaches are analysed based on the requirements composed by fundamental objectives of EMAG simulations and AFM-specific effects, revealing limitations in flexibility and the ability to capture emerging trends in the field of AFMs. While computationally expensive 3D finite element analysis (FEA) offers comprehensive flexibility in EMAG modelling, it lacks efficiency to carry out extensive studies on such trends. Therefore, there is a need to either further accelerate 3D FEA or to increase the flexibility of existing alternatives to facilitate and thereby promote research in the field of AFM and other 3D flux machines. While the integration of some production-specific effects, such as manufacturing tolerances, already is investigated for EMAG simulations of AFMs the future research on the early estimation of manufacturability based on EMAG simulations is crucial for evaluating designs and anticipating manufacturing influences.
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    Optimal transistor dimensioning in T-type topology for reduced quasi-2-level switching loss
    (2025) Söllner, Adrian; Jie, Chengcong; Mönch, Stefan
    A quasi-2-level switching T-type topology reduces hard-switching loss compared to half-bridges, but requires more semiconductor area. This work shows that the middle transistor can be dimensioned smaller than the high/low-side transistors, which further reduces both the switch node capacitance and switching loss. The paper also presents a scalable transistor model, which is used in simulations of inductive-load hard-switching to determine switching losses and reveal a loss-optimal transistor dimensioning. Furthermore a double pulse setup (600 V-rated GaN HEMTs in a T-type topology) with 2 ground referenced shunts is proposed to determine switching energy of middle and low side transistors simultaneously. To verify the concept of loss-optimal transistor dimensioning in Q2L T-type topology, switching energy was measured at 200 V and 1 A, with the middle transistors area reduced by half compared to high/low side, resulting in a measured reduction from 4.44 µJ to 2.18 µJ (-51%) which is similar to the simulated reduction (2.39 µJ to 1.43 µJ, -40%). This method allows reduction of Q2L switching-loss with optimal transistor area and can be used for a wide range of applications.