05 Fakultät Informatik, Elektrotechnik und Informationstechnik
Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6
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Item Open Access Modeling and investigating total ionizing dose impact on FeFET(2023) Sayed, Munazza; Ni, Kai; Amrouch, HussamItem Open Access Thermal effects on monolithic 3D ferroelectric transistors for deep neural networks performance(2024) Kumar, Shubham; Chauhan, Yogesh Singh; Amrouch, HussamMonolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.Item Open Access Review on resistive switching devices based on multiferroic BiFeO3(2023) Zhao, Xianyue; Menzel, Stephan; Polian, Ilia; Schmidt, Heidemarie; Du, NanThis review provides a comprehensive examination of the state-of-the-art research on resistive switching (RS) in BiFeO3 (BFO)-based memristive devices. By exploring possible fabrication techniques for preparing the functional BFO layers in memristive devices, the constructed lattice systems and corresponding crystal types responsible for RS behaviors in BFO-based memristive devices are analyzed. The physical mechanisms underlying RS in BFO-based memristive devices, i.e., ferroelectricity and valence change memory, are thoroughly reviewed, and the impact of various effects such as the doping effect, especially in the BFO layer, is evaluated. Finally, this review provides the applications of BFO devices and discusses the valid criteria for evaluating the energy consumption in RS and potential optimization techniques for memristive devices.Item Open Access Benchmarking the performance of portfolio optimization with QAOA(2022) Brandhofer, Sebastian; Braun, Daniel; Dehn, Vanessa; Hellstern, Gerhard; Hüls, Matthias; Ji, Yanjun; Polian, Ilia; Bhatia, Amandeep Singh; Wellens, ThomasWe present a detailed study of portfolio optimization using different versions of the quantum approximate optimization algorithm (QAOA). For a given list of assets, the portfolio optimization problem is formulated as quadratic binary optimization constrained on the number of assets contained in the portfolio. QAOA has been suggested as a possible candidate for solving this problem (and similar combinatorial optimization problems) more efficiently than classical computers in the case of a sufficiently large number of assets. However, the practical implementation of this algorithm requires a careful consideration of several technical issues, not all of which are discussed in the present literature. The present article intends to fill this gap and thereby provides the reader with a useful guide for applying QAOA to the portfolio optimization problem (and similar problems). In particular, we will discuss several possible choices of the variational form and of different classical algorithms for finding the corresponding optimized parameters. Viewing at the application of QAOA on error-prone NISQ hardware, we also analyse the influence of statistical sampling errors (due to a finite number of shots) and gate and readout errors (due to imperfect quantum hardware). Finally, we define a criterion for distinguishing between ‘easy’ and ‘hard’ instances of the portfolio optimization problem.Item Open Access Mixed-mode in-memory computing : towards high-performance logic processing in a memristive crossbar array(2025) Du, Nan; Polian, Ilia; Bengel, Christopher; Li, Kefeng; Chen, Ziang; Zhao, Xianyue; Hübner, Uwe; Chen, Li-Wei; Liu, Feng; Di Ventra, Massimiliano; Menzel, Stephan; Krüger, HeidemarieIn-memory computing is a promising alternative to traditional computer designs, as it helps overcome performance limits caused by the separation of memory and processing units. However, many current approaches struggle with unreliable device behavior, which affects data accuracy and efficiency. In this work, the authors present a new computing method that combines two types of operations—those based on electrical resistance and those based on voltage-within each memory cell. This design improves reliability and avoids the need for expensive current measurements. A new software tool also helps automate the design process, supporting highly parallel operations in dense two-dimensional memory arrays. The approach balances speed and space, making it practical for advanced computing tasks. Demonstrations include a digital adder and a key part of encryption module, showing both strong performance and accuracy. This work offers a new direction for reliable and efficient in-memory computing systems with real-world applications.Item Open Access Nontraditional design of dynamic logics using FDSOI for ultra-efficient computing(2023) Kumar, Shubham; Chatterjee, Swetaki; Dabhi, Chetan Kumar; Chauhan, Yogesh Singh; Amrouch, HussamItem Open Access Small delay fault testing with multiple voltages under variations : defect vs. fault coverage(2025) Jafarzadeh, Hanieh; Klemme, Florian; Amrouch, Hussam; Hellebrand, Sybille; Wunderlich, Hans-JoachimIt has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that Vmintesting poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under Vminis a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first algorithm for test pattern generation specifically tuned for Vmintesting which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. The patterns applicable to other voltage levels can be derived from the pattern set generated under extreme variations at low supply voltage. Experimental results demonstrate that the proposed method produces test patterns that outperform N-detection test sets in terms of test set volume and fault efficiency across different voltage levels.Item Open Access Stress-aware periodic test of interconnects(2022) Sadeghi-Kohan, Somayeh; Hellebrand, Sybille; Wunderlich, Hans-JoachimSafety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.Item Open Access Physics inspired compact modelling of BiFeO3 based memristors(2022) Yarragolla, Sahitya; Du, Nan; Hemke, Torben; Zhao, Xianyue; Chen, Ziang; Polian, Ilia; Mussenbrock, ThomasWith the advent of the Internet of Things, nanoelectronic devices or memristors have been the subject of significant interest for use as new hardware security primitives. Among the several available memristors, BiFe O3 (BFO)-based electroforming-free memristors have attracted considerable attention due to their excellent properties, such as long retention time, self-rectification, intrinsic stochasticity, and fast switching. They have been actively investigated for use in physical unclonable function (PUF) key storage modules, artificial synapses in neural networks, nonvolatile resistive switches, and reconfigurable logic applications. In this work, we present a physics-inspired 1D compact model of a BFO memristor to understand its implementation for such applications (mainly PUFs) and perform circuit simulations. The resistive switching based on electric field-driven vacancy migration and intrinsic stochastic behaviour of the BFO memristor are modelled using the cloud-in-a-cell scheme. The experimental current–voltage characteristics of the BFO memristor are successfully reproduced. The response of the BFO memristor to changes in electrical properties, environmental properties (such as temperature) and stress are analyzed and consistant with experimental results.Item Open Access Memristive true random number generator for security applications(2024) Zhao, Xianyue; Chen, Li-Wei; Li, Kefeng; Schmidt, Heidemarie; Polian, Ilia; Du, NanThis study explores memristor-based true random number generators (TRNGs) through their evolution and optimization, stemming from the concept of memristors first introduced by Leon Chua in 1971 and realized in 2008. We will consider memristor TRNGs coming from various entropy sources for producing high-quality random numbers. However, we must take into account both their strengths and weaknesses. The comparison with CMOS-based TRNGs will serve as an illustration that memristor TRNGs stand out due to their simpler circuits and lower power consumption- thus leading us into a case study involving electroless YMnO3 (YMO) memristors as TRNG entropy sources that demonstrate good security properties by being able to produce unpredictable random numbers effectively. The end of our analysis sees us pinpointing challenges: post-processing algorithm optimization coupled with ensuring reliability over time for memristor-based TRNGs aimed at next-generation security applications.