05 Fakultät Informatik, Elektrotechnik und Informationstechnik
Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6
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Item Open Access Development of an error detection and recovery technique for a SPARC V8 processor in FPGA technology(2011) Boktor, AndrewField-Programmable Gate Arrays (FPGAs) found widespread use in many areas of applications, including safety and mission-critical systems. More and more manufacturers are choosing to implement designs on FPGAs. However, SRAM-based FPGAs are proven to be much more prone to Single Event Upsets (SEUs) compared to traditional Application-Specific Integrated Circuit (ASIC) designs. Moreover, SEU affects FPGAs in more severe ways compared to ASIC. Techniques to provide fault-tolerance for SRAM-based FPGAs become essential to maintain their advantages over other technologies. This thesis presents a fault-tolerance technique for pipeline architectures in FPGA technology. It provides fault-tolerance against SEUs in the design and is able to detect faults in the FPGA configuration. It also proposes an additional mechanism that detects all SEUs independent of their location. Pipeline operation can be resumed with known techniques of partial reconfiguration. Both designs occupy a much smaller area compared to known techniques such as TMR in combination with Scrubbing. They introduce no additional time penalty in case of fault-free operation. Fault injection and simulation were used to validate the design and calculate the fault coverage.Item Open Access Efficient programmable deterministic self-test(2010) Hakmi, Abdul-Wahid; Wunderlich, Hans-Joachim (Prof. Dr. habil.)In modern times, integrated circuits (ICs) are used in almost all electronic equipment ranging from household appliances to space shuttles and have revolutionized the world of electronics. Continuous reductions in the manufacturing costs as well as the size of this technology have allowed the development of very sophisticated ICs for common use. Post fabrication testing is necessary for each IC in order to ensure the quality and the safety of human life. The improvement in technology as well as economies of scale are continuously reducing fabrication costs. On the other hand, the increasing complexity of circuits is leading to higher test costs. These increasing test costs affect the market price of a chip. A test set is a set of binary patterns that are applied on the circuit inputs to detect the potential faults. Only a small number of bits in a test set are specified to 0 or 1 called care bits while other bits called don't care bits may assume random values. Test sets volume is characterized by the number of patterns as well as the size of each pattern in a test set. The increasing number of gates in nanometer ICs has resulted in an explosive increase in test sets volume. This increase in test sets volume is the major cause for rapidly growing test costs. An IC is tested either by using an automatic test equipment (ATE) or with the help of special hardware added on-chip that performs a self-test. These two approaches as well as their hybrid derivatives offer various trade-offs in test costs, quality, reliability and test time. In ATE testing high test sets volume leads to the requirement of expensive testers with large storage capacity while in self-test it results in significant hardware overhead. A test set is highly compressible due to the presence of a large number of don't care bits. The Test data compression techniques are used to limit test sets volume and hence the involved test cost. These compressed test sets are applicable to both ATE and Self-test methodologies. Compression of a test set depends on its statistical attributes such as the percentage and the distribution of care bits. The available test compression schemes assume that all the test sets have similar statistical attributes which is not always true. These attributes vary considerably among various test sets depending on the circuit structure and the targeted trade-offs. To get optimized reduction in test sets volume, test sets with different statistical attributes have to be addressed separately. In this work we analyze various test sets of industrial circuits and categorize them into three classes based on their statistical attributes. By examining each class differently, three novel compression methods and decompression architectures are proposed. The proposed test compression methods are equally adaptable in ATE testing and self-test. Three low cost programmable self-test schemes offering various trade-offs in testing are developed by applying these methods. The experimental results obtained with the test sets of large industrial circuits show that the proposed compression methods reduce storage requirements by more than half compared to the most efficient available methods. First time in literature the total number of bits in a compressed test set are lesser than the number of care bits in the original test set. The additional advantages of proposed methods include guaranteed encoding, significant reduction in decompression time overhead and programmability of decompression hardware.Item Open Access Software based self test under memory, time and power constraints(2009) Zhou, Jun; Wunderlich, Hans-Joachim (Prof. Dr. habil.)The use of embedded system is ubiquitous in modern life, from automotive industry, robot techniques to the household appliances. As the core component of embedded systems, microprocessors play the central role in information processing, and fulfill several specialized tasks. The involvment in safty-critical applications requires high reliability of these systems. Test is known to be important for product quality and used to detect defects both during manufacturing or in-field scenario. In particular, the following aspects are crucial for microprocessor test. First, a low-cost test is preferrable in terms of hardware overhead, test time for example. To detect timing faults, testing at the system frequency, namely at-speed testing, is required. Design modification to incorporate hardware dedicated for test is not desirable due to potential performance degradation. Overtesting accounts for possible yield loss in that chips may fail the structural test, although those faults can never be sensitized in normal functional operations. The advent of software-based self-test solve these problems and therefore becomes the target of this work. However, constrained test generation is still of need. The dissertation looks into this aspect and proposes a novel SBST scheme, which optimizes memory, test application and power consumption at the same time without penalty of fault coverage. In addition, this work also presents a method to improve test quality of SBST through adding new instructions under the ASIP (application-specific instruction-set processor) framework.Item Open Access Simulation of realistic defects for validating test- and diagnosis-algorithms(2011) Atali, Hossam elTesting and diagnosis are very important in the manufacture of Integrated Circuits (ICs) due to the decrease in technology size. Diagnosis aims to detect and localize faults and obtain information about them and many diagnosis algorithms exist for that purpose. These diagnosis algorithms, however, apply heuristics and therefore must be evaluated with realistic test cases to determine their efficiency. The goal of this thesis is to obtain a realistic set of bridging faults to inject for evaluation of the diagnosis algorithm presented by Holst in the ADAMA tool. To achieve this, the multi-node inductive fault analysis algorithm presented by Zachariah and Chakravarty was implemented. Multi-node bridging fault lists were obtained and passed to ADAMA for diagnosis. Simulations were run on several circuits and the results of the inductive fault analysis were compared to those obtained from random fault generation.Item Open Access CUDA-accelerated delay fault simulation(2011) Schneider, EricIn todays VLSI chip manufacturing processes variations occur, that may manifest as delay defects and affect the timing behaviour of the circuit. In general, these delay faults only occur under at-speed test conditions and it requires special effort to simulate them. Since fault simulation is inherently parallelizable, NVIDIAs Compute Unified Device Architecture (CUDA) is used for utilizing general purpose graphics processing units (GPGPUs) in order to exploit available parallelism. The goal of this study thesis was the implementation of a delay fault simulator to simulate the behaviour of small delay faults on CUDA devices and its integration into a diagnosis framework for application of the Partially Overlapping Impact couNTER (POINTER) algorithm. A series of experiments was performed to observe the diagnosability of the delay faults.Item Open Access Implementing density functional theory (DFT) methods on many-core GPGPU accelerators(2011) Gosswami, Bishwajit MohanDensity Functional Theory (DFT) is one of the most widely used quantum mechanical methods for calculations of the electronic structure of molecules and surfaces, which achieves an excellent balance of accuracy and computational cost. However, for large molecular systems with few hundred atoms, the computational costs are become very high. Therefore, there is a fast growing demand for much more efficient implementations to utilize DFT for macro molecules. General Purpose Graphics Processors (GPUs) are highly parallel, multi-threaded, many-core processors with tremendous computational capability, which out-paces CPUs in terms of floating-point performance. They are particularly focused for computation intensive and highly data-parallel computations. This thesis will introduce the scope of fine grained parallelism with highly data-parallel GPU implementations of several algorithmic parts of DFT. Furthermore, experimental results and benchmarks will be presented in comparison with a current state of art DFT implementation (Molpro).Item Open Access Strukturelle Feldtests komplexer ASICs(2011) Ull, DominikIn dieser Ausarbeitung wird ein zerstörungsfreier Befundungstest für Kfz-Steuergeräte vorgestellt. Hersteller von Automobilelektronik können bisher nicht nachweisen, dass ein an den Kfz-Hersteller ausgeliefertes Steuergerät wirklich fehlerfrei ist, obwohl zur Minimierung des Testaufwands bei der Produktion der enthaltenen ASICs (Application Specific ICs) schon während der Entwicklungsphase des Chipdesigns strukturelle, standardisierte Testmethoden und eingebaute Selbsttests (BIST, Built-In Self-Test) integriert werden. Es soll nun beispielhaft an einem ASIC aufgezeigt werden, in wie weit diese Methoden beim strukturellen Feldtest von Automobil-Steuergeräten - im Rahmen eines zerstörungsfreien Befundungstests von Feldrückläufern - Verwendung finden. Der Test ermöglicht neben der Klärung teurer Garantieansprüche auch eine verlässliche Informationsquelle für ein eventuelles Redesign. Durch die Implementierung des JTAG-Protokolls auf den Signalleitungen des steuergerät-internen SPI-Bus können ASIC-interne Selbsttests für Speicher und Analog-Digital-Converter (ADC) im verbauten Zustand ausgeführt werden. Die softwarebasierte Anwendung von Scan Patterns auf Steuergerät-Ebene ermöglicht einen einfachen Scan Test für ASICs ohne Logik-BIST. Es folgt ein Realisierungsvorschlag zur Prüfung aller steuergerät-internen Taktquellen, um die durch Kombination von BIST und softwarebasierten Methoden erreichbare Testabdeckung aufzuzeigen.Item Open Access Evaluation of backtracing based diagnosis algorithms(2011) Badreldein, MahaWith the growing size and complexity of modern circuits, more algorithms are being developed nowadays for efficient fault diagnosis. Backtracing based diagnosis algorithms are effect-cause approaches that start from the failing outputs of the circuit and try to diagnose fault locations by backtracing lines toward the circuit inputs. In this thesis, general functionality was extracted between backtracing based diagnosis algorithms and implemented as an extension to an existing diagnosis framework. Furthermore, a simple graphical user interface was developed for the extended framework. The extended framework aims at facilitating the implementation and evaluation of different backtracing based diagnosis algorithms. In order to demonstrate its powerfulness, two modern backtracing based diagnosis algorithms were implemented on top of the extended framework. A number of diagnosis experiments on benchmark circuits was carried out in order to evaluate the two implemented algorithms. The experimental tools used and the results obtained are presented.Item Open Access Scalable deterministic logic built-in self test(2006) Gherman, Valentin; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat.)The core-based design style of integrated circuits (ICs) helps to manage the development challenges brought by the ever increasing complexity of integrated systems and the ever tighter time-to-market. Nevertheless, test-related problems are still far away from having a unitary and satisfactory solution, especially in the system on a chip (SOC) context. For the test of ICs two reference approaches are available: external testing and built-in selftest (BIST), out of which a variety of hybrid test strategies are obtained by test resource partitioning (TRP). The final goal is to provide advantageous tradeoffs of the test evaluation indicators like: test development and application cost, hardware overhead, fault coverage, etc. BIST offers support for in-field, on-line, burn-in and at-speed test that is indispensable for delay fault testing. Moreover, tradeoffs between fault coverage, hardware overhead and test length are possible. External testing is characterized by flexibility, reduced hardware overhead and high fault coverage for a given test length. Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines the advantages of deterministic external testing and pseudo-random logic BIST (LBIST). Unfortunately, previously proposed DLBIST methods are unsuited for large ICs, since computation time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this work, a novel procedure for the development of the so-called bit-flipping DLBIST scheme is proposed, which has nearly linear complexity in terms of both computation time and memory consumption. This new method is based on the use of Binary Decision Diagrams (BDDs). The efficiency of the employed algorithms is demonstrated for industrial designs containing up to 2M gates. The embedded test sequences obtained by mapping deterministic cubes to pseudo-random sequences are also evaluated with respect to the coverage of non-target defects, which are modeled with the help of resistive bridging faults. The experimental results prove that both deterministic cubes and pseudo-random sequences are useful for detecting non-target defects. Moreover, possible tradeoffs between test length, hardware overhead, fault coverage and nontarget defect coverage are analyzed. This work additionally presents the results of extending the bit-flipping DLBIST scheme such that it also supports the transition fault testing besides the stuck-at fault testing. Transition faults model defects which are responsible for the incorrect operation of the core under test (CUT) at the desired speed. The importance of these defects is continuously enhanced by the ever increasing clock rates and integration density of today s circuits. Experimental results obtained for large industrial benchmark designs are reported. No pure DLBIST approach for the test of delay faults in circuits with standard scan design has been published so far. In order to decrease the logic overhead of DLBIST, an innovative way of constructing efficient implementations for the involved Boolean functions (e.g. bit-flipping functions) is presented. A key feature of these functions is their incomplete specification which is based on large don t care sets (sets of input assignments for which it does not matter whether they are mapped to 0 or 1 ). Reduced ordered Binary Decision Diagrams (ROBDD) are used for representing and manipulating the involved functions and multi-level implementations are obtained based on the use of free BDDs (FBDD). Experimental results show that for all the considered functions, implementations are found with a significant reduction of the gate count as compared to a state-of-the-art multi-level synthesys tool (SIS [Sen92]) or to methods offered by a state-of-the-art BDD package. This performance is due to a reduction of the node count in the corresponding FBDDs and a decrease in the average number of gates needed to implement the FBDD nodes. The experimental results obtained for large industrial benchmark designs show that DLBIST may be well suited for use in special segments of IC development, like the ones dealing with security chips or hard cores.Item Open Access Evaluation of advanced techniques for structural FPGA self-test(2011) Abdelfattah, MohamedThis thesis presents a comprehensive test generation framework for FPGA logic elements and interconnects. It is based on and extends the current state-of-the-art. The purpose of FPGA testing in this work is to achieve reliable reconfiguration for a FPGA-based runtime reconfigurable system. A pre-configuration test is performed on a portion of the FPGA before it is reconfigured as part of the system to ensure that the FPGA fabric is fault-free. The implementation platform is the Xilinx Virtex-5 FPGA family. Existing literature in FPGA testing is evaluated and reviewed thoroughly. The various approaches are compared against one another qualitatively and the approach most suitable to the target platform is chosen. The array testing method is employed in testing the FPGA logic for its low hardware overhead and optimal test time. All tests are additionally pipelined to reduce test application time and use a high test clock frequency. A hybrid fault model including both structural and functional faults is assumed. An algorithm for the optimization of the number of required FPGA test configurations is developed and implemented in Java using a pseudo-random set-covering heuristic. Optimal solutions are obtained for Virtex-5 logic slices. The algorithm effort is parameterizable with the number of loop iterations each of which take approximately one second for a Virtex-5 sliceL circuit. A flexible test architecture for interconnects is developed. Arbitrary wire types can be tested in the same test configuration with no hardware overhead. Furthermore, a routing algorithm is integrated with the test template generation to select the wires under test and route them appropriately. Nine test configurations are required to achieve full test coverage for the FPGA logic. For interconnect testing, a local router-based on depth-first graph traversal is implemented in Java as the basis for creating systematic interconnect test templates. Pent wire testing is additionally implemented as a proof of concept. The test clock frequency for all tests exceeds 170 MHz and the hardware overhead is always lower than seven CLBs. All implemented tests are parameterizable such that they can be applied to any portion of the FPGA regardless of size or position.