05 Fakultät Informatik, Elektrotechnik und Informationstechnik

Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6

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Institute: search.filters.UBSInstitut.Institut für Technische InformatikStart date: 2011End date: 2011Subject: search.filters.subject.004

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Now showing 1 - 7 of 7
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    Development of an error detection and recovery technique for a SPARC V8 processor in FPGA technology
    (2011) Boktor, Andrew
    Field-Programmable Gate Arrays (FPGAs) found widespread use in many areas of applications, including safety and mission-critical systems. More and more manufacturers are choosing to implement designs on FPGAs. However, SRAM-based FPGAs are proven to be much more prone to Single Event Upsets (SEUs) compared to traditional Application-Specific Integrated Circuit (ASIC) designs. Moreover, SEU affects FPGAs in more severe ways compared to ASIC. Techniques to provide fault-tolerance for SRAM-based FPGAs become essential to maintain their advantages over other technologies. This thesis presents a fault-tolerance technique for pipeline architectures in FPGA technology. It provides fault-tolerance against SEUs in the design and is able to detect faults in the FPGA configuration. It also proposes an additional mechanism that detects all SEUs independent of their location. Pipeline operation can be resumed with known techniques of partial reconfiguration. Both designs occupy a much smaller area compared to known techniques such as TMR in combination with Scrubbing. They introduce no additional time penalty in case of fault-free operation. Fault injection and simulation were used to validate the design and calculate the fault coverage.
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    CUDA-accelerated delay fault simulation
    (2011) Schneider, Eric
    In todays VLSI chip manufacturing processes variations occur, that may manifest as delay defects and affect the timing behaviour of the circuit. In general, these delay faults only occur under at-speed test conditions and it requires special effort to simulate them. Since fault simulation is inherently parallelizable, NVIDIAs Compute Unified Device Architecture (CUDA) is used for utilizing general purpose graphics processing units (GPGPUs) in order to exploit available parallelism. The goal of this study thesis was the implementation of a delay fault simulator to simulate the behaviour of small delay faults on CUDA devices and its integration into a diagnosis framework for application of the Partially Overlapping Impact couNTER (POINTER) algorithm. A series of experiments was performed to observe the diagnosability of the delay faults.
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    Implementing density functional theory (DFT) methods on many-core GPGPU accelerators
    (2011) Gosswami, Bishwajit Mohan
    Density Functional Theory (DFT) is one of the most widely used quantum mechanical methods for calculations of the electronic structure of molecules and surfaces, which achieves an excellent balance of accuracy and computational cost. However, for large molecular systems with few hundred atoms, the computational costs are become very high. Therefore, there is a fast growing demand for much more efficient implementations to utilize DFT for macro molecules. General Purpose Graphics Processors (GPUs) are highly parallel, multi-threaded, many-core processors with tremendous computational capability, which out-paces CPUs in terms of floating-point performance. They are particularly focused for computation intensive and highly data-parallel computations. This thesis will introduce the scope of fine grained parallelism with highly data-parallel GPU implementations of several algorithmic parts of DFT. Furthermore, experimental results and benchmarks will be presented in comparison with a current state of art DFT implementation (Molpro).
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    Evaluation of backtracing based diagnosis algorithms
    (2011) Badreldein, Maha
    With the growing size and complexity of modern circuits, more algorithms are being developed nowadays for efficient fault diagnosis. Backtracing based diagnosis algorithms are effect-cause approaches that start from the failing outputs of the circuit and try to diagnose fault locations by backtracing lines toward the circuit inputs. In this thesis, general functionality was extracted between backtracing based diagnosis algorithms and implemented as an extension to an existing diagnosis framework. Furthermore, a simple graphical user interface was developed for the extended framework. The extended framework aims at facilitating the implementation and evaluation of different backtracing based diagnosis algorithms. In order to demonstrate its powerfulness, two modern backtracing based diagnosis algorithms were implemented on top of the extended framework. A number of diagnosis experiments on benchmark circuits was carried out in order to evaluate the two implemented algorithms. The experimental tools used and the results obtained are presented.
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    Strukturelle Feldtests komplexer ASICs
    (2011) Ull, Dominik
    In dieser Ausarbeitung wird ein zerstörungsfreier Befundungstest für Kfz-Steuergeräte vorgestellt. Hersteller von Automobilelektronik können bisher nicht nachweisen, dass ein an den Kfz-Hersteller ausgeliefertes Steuergerät wirklich fehlerfrei ist, obwohl zur Minimierung des Testaufwands bei der Produktion der enthaltenen ASICs (Application Specific ICs) schon während der Entwicklungsphase des Chipdesigns strukturelle, standardisierte Testmethoden und eingebaute Selbsttests (BIST, Built-In Self-Test) integriert werden. Es soll nun beispielhaft an einem ASIC aufgezeigt werden, in wie weit diese Methoden beim strukturellen Feldtest von Automobil-Steuergeräten - im Rahmen eines zerstörungsfreien Befundungstests von Feldrückläufern - Verwendung finden. Der Test ermöglicht neben der Klärung teurer Garantieansprüche auch eine verlässliche Informationsquelle für ein eventuelles Redesign. Durch die Implementierung des JTAG-Protokolls auf den Signalleitungen des steuergerät-internen SPI-Bus können ASIC-interne Selbsttests für Speicher und Analog-Digital-Converter (ADC) im verbauten Zustand ausgeführt werden. Die softwarebasierte Anwendung von Scan Patterns auf Steuergerät-Ebene ermöglicht einen einfachen Scan Test für ASICs ohne Logik-BIST. Es folgt ein Realisierungsvorschlag zur Prüfung aller steuergerät-internen Taktquellen, um die durch Kombination von BIST und softwarebasierten Methoden erreichbare Testabdeckung aufzuzeigen.
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    Simulation of realistic defects for validating test- and diagnosis-algorithms
    (2011) Atali, Hossam el
    Testing and diagnosis are very important in the manufacture of Integrated Circuits (ICs) due to the decrease in technology size. Diagnosis aims to detect and localize faults and obtain information about them and many diagnosis algorithms exist for that purpose. These diagnosis algorithms, however, apply heuristics and therefore must be evaluated with realistic test cases to determine their efficiency. The goal of this thesis is to obtain a realistic set of bridging faults to inject for evaluation of the diagnosis algorithm presented by Holst in the ADAMA tool. To achieve this, the multi-node inductive fault analysis algorithm presented by Zachariah and Chakravarty was implemented. Multi-node bridging fault lists were obtained and passed to ADAMA for diagnosis. Simulations were run on several circuits and the results of the inductive fault analysis were compared to those obtained from random fault generation.
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    Evaluation of advanced techniques for structural FPGA self-test
    (2011) Abdelfattah, Mohamed
    This thesis presents a comprehensive test generation framework for FPGA logic elements and interconnects. It is based on and extends the current state-of-the-art. The purpose of FPGA testing in this work is to achieve reliable reconfiguration for a FPGA-based runtime reconfigurable system. A pre-configuration test is performed on a portion of the FPGA before it is reconfigured as part of the system to ensure that the FPGA fabric is fault-free. The implementation platform is the Xilinx Virtex-5 FPGA family. Existing literature in FPGA testing is evaluated and reviewed thoroughly. The various approaches are compared against one another qualitatively and the approach most suitable to the target platform is chosen. The array testing method is employed in testing the FPGA logic for its low hardware overhead and optimal test time. All tests are additionally pipelined to reduce test application time and use a high test clock frequency. A hybrid fault model including both structural and functional faults is assumed. An algorithm for the optimization of the number of required FPGA test configurations is developed and implemented in Java using a pseudo-random set-covering heuristic. Optimal solutions are obtained for Virtex-5 logic slices. The algorithm effort is parameterizable with the number of loop iterations each of which take approximately one second for a Virtex-5 sliceL circuit. A flexible test architecture for interconnects is developed. Arbitrary wire types can be tested in the same test configuration with no hardware overhead. Furthermore, a routing algorithm is integrated with the test template generation to select the wires under test and route them appropriately. Nine test configurations are required to achieve full test coverage for the FPGA logic. For interconnect testing, a local router-based on depth-first graph traversal is implemented in Java as the basis for creating systematic interconnect test templates. Pent wire testing is additionally implemented as a proof of concept. The test clock frequency for all tests exceeds 170 MHz and the hardware overhead is always lower than seven CLBs. All implemented tests are parameterizable such that they can be applied to any portion of the FPGA regardless of size or position.