05 Fakultät Informatik, Elektrotechnik und Informationstechnik

Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6

Browse

Filters

2022 - 20242

Settings

Publication Type: search.filters.UBSTyp.DissertationStart date: 2020Institute: search.filters.UBSInstitut.Institut für Technische InformatikSubject: search.filters.subject.620

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    ItemOpen Access
    Dependable reconfigurable scan networks
    (2022) Lylina, Natalia; Wunderlich, Hans-Joachim (Prof.)
    The dependability of modern devices is enhanced by integrating an extensive number of extra-functional instruments. These are needed to facilitate cost-efficient bring-up, debug, test, diagnosis, and adaptivity in the field and might include, e.g., sensors, aging monitors, Logic, and Memory Built-In Self-Test (BIST) registers. Reconfigurable Scan Networks (RSNs) provide a flexible way to access such instruments as well the device's registers throughout the lifetime, starting from post-silicon validation (PSV) through manufacturing test and finally during in-field operation. At the same time, the dependability properties of the system can be affected through an improper RSN integration. This doctoral project overcomes these problems and establishes a methodology to integrate dependable RSNs for a given system considering the most relevant dependability aspects, such as robustness, testability, and security compliance of RSNs.
  • Thumbnail Image
    ItemOpen Access
    Brain-inspired hyperdimensional computing for robust and lightweight machine learning
    (2024) Genssler, Paul R.; Amrouch, Hussam (Prof. Dr.-Ing.)
    This thesis investigates hyperdimensional computing (HDC) as an emerging machine learning method. HDC’s integration with in-memory computing architectures is explored to address challenges at both application and technology levels, particularly in the domain of semiconductor test and reliability. HDC’s inherent redundancy offers robustness to errors, making it suitable for applications like transistor aging modeling, circuit recognition, and wafer map defect pattern classification. However, it is computationally demanding for off-the-shelf systems, motivating the development of efficient architectures using FPGA, custom chips, and FeFET-based in-memory computing. This integration bridges the gap between technology and application levels, enhancing efficiency while addressing reliability trade-offs. The work also adapts HDC training to mitigate errors from non-volatile memories, ensuring robust performance. Overall, the thesis demonstrates HDC’s potential for lightweight, efficient ML systems and novel applications, overcoming limitations of traditional approaches.