05 Fakultät Informatik, Elektrotechnik und Informationstechnik
Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6
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Item Open Access Molekularstrahlepitaxie und Charakterisierung unverspannter Silizium-Germanium-Zinn-Legierungen auf virtuellem Germanium-Substrat(2022) Schwarz, Daniel; Schulze, Jörg (Prof. Dr. habil.)Item Open Access Low-complexity adaptive digital equalizers for electronic dispersion compensation in optical fiber links(2022) Efinger, Daniel; Speidel, Joachim (Prof. Dr.-Ing.)This thesis addresses electronic equalization of intersymbol interference caused by chromatic and polarization mode dispersion in intensity-modulated optical communication links with direct detection. The simple and cost-efficient system setup is, even at high bit rates of 40 Gbit/s and beyond, of interest for short-haul optical links in metropolitan, aggregation or local area networks. Therefore, this thesis investigates preferably simple and low-complexity equalizer structures, which are able to compensate well for the nonlinear characteristics and influences of the intensity-modulated optical communication link with direct detection. Starting with system modeling and the introduction to different equalization methods, we identify low-complexity feed-forward and decision-feedback equalizers in the first part of this thesis. We further put their chromatic and polarization mode dispersion compensation performance to the broader context by comparison to maximum likelihood sequence estimation. Finally, we come to the investigation of adaptation algorithms for equalizer coefficient adjustment, which accounts for the time-variant nature of polarization mode dispersion, while still targeting preferably simple and efficient realization.Item Open Access Novel characterization techniques for the study of the dynamic behavior of silicon carbide power MOSFETs(2022) Salcines, Cristino; Kallfass, Ingmar (Prof. Dr.-Ing.)This dissertation provides insight into the dynamic behavior of SiC power MOSFETs from their inherent static IV and CV characteristics. While conventional dynamic measurements extracted from a DPT or a similar dynamic test-bench yield accurate quantitative data, the static IV and CV characteristics of a power semiconductor device offer more qualitative information to delve into the root mechanisms responsible for its dynamic behavior. Conventional characterization techniques are limited to power levels way below those which the power device withstands in the application. As a result, the static IV and CV characteristics attained by available measurement solutions are reduced to a limited scope of bias conditions insufficient to infer information about the dynamic behavior of the power device. This work tackles this gap and proposes novel measurement techniques that enable the characterization of the static IV and CV characteristics of SiC power MOSFETs at the full range of bias conditions the power device goes through in the application. Iso-thermal IV characteristics of a commercially available SiC power MOSFET are measured up to 40 kW power (instantaneous 50 A and 800 V) at junction temperatures ranging from 25°C to 175 °C. The CV characteristics are mapped at drain-source and gate-source bias combinations of VDS = 0 - 40 V and VGS = 0 - 20 V, respectively, at junction temperatures ranging from 25°C to 150 °C. The results of these measurements reveal unique insights into the electrical characteristics of SiC power MOSFETs which impact their performance in the application and explain unclear phenomena observed in their dynamic behavior. On the one hand, the intrinsic capacitances of the SiC power MOSFET extend their non-linearity, function of both VGS and VDS, to the saturation region of the power device. Moreover, they are also affected by the junction temperature of the power device. The impact of these in the voltage commutation speed of the device under different switching conditions is thoroughly analyzed in the thesis. On the other hand, the IV characteristics of the SiC power MOSFET reveal the existence of short channel effects that drastically affect the transconductance of the power device in its high voltage saturation region. Furthermore, the measurements show a positive temperature coefficient of the drain current in the high voltage saturation region of the SiC power device, attributed to the density of trap energy states in the SiC/SiO2 interface. These effects effectively lower the plateau voltage of the device and lead to faster current commutation speeds in the application than those expected from the datasheet values. The insights revealed by the proposed characterization techniques are intended to help fine-tune semiconductor technology processes and improve the accuracy of simulation models to achieve a higher grade of optimization in the design of future SiC-based energy conversion circuits.Item Open Access Design of frequency-converting monolithic integrated circuits for millimeter-wave applications(2022) Grötsch, Christopher; Kallfass, Ingmar (Prof. Dr.-Ing.)This thesis focuses on how to efficiently utilize the low terahertz spectrum in the frequency range from 220 to 325 GHz, also called H-band. This work presents an introduction on several techniques necessary for designing frequency-converting monolithic millimeter-wave integrated circuits for this frequency range. Six different frequency-converter MMICs in a 35 nm gate-length InGaAs mHEMT technology are presented: a nonlinear resistance up- and down-converter, a dual-gate up and down-converter, a gate-pumped transconductance up-converter and a half Gilbert cell up-converter. Each design is explained in detail, their advantages and their disadvantages are evaluated. Three examples will be given where a selection of the frequency-converter architectures are integrated with other functional stages like frequency multipliers and amplifiers to form a millimeter-wave transceiver: a highly linear FMCW radar receiver with a 50 GHz bandwidth, a heterodyne communication receiver facilitating multi-channel transmissions with carrier aggregation at W-band and a homodyne communication receiver with an integrated antenna for low-cost assembly on a PCB. Thereby, this thesis provides insight into the design considerations of terahertz frequency converters, the trade-off of different circuit architectures and topologies for certain applications, the obstacles that can occur during their development and approaches to overcome them.Item Open Access Parallel-Analog/Digital-Umsetzer für Gigabaud-Applikationen(2021) Du, Xuan-Quang; Berroth, Manfred (Prof. Dr.-Ing.)Communication systems with digital signal processors (DSPs) rely on data converters as interface blocks between the analog and the digital domain. The channel data rates in these systems can be increased by choosing a higher symbol rate and/or a more complex modulation format. Both approaches motivate the design of data converters with high sample rates and/or high effective bit resolution. As the improvement of the converter linearity in terms of power efficiency is more difficult to realize, especially at high operation frequencies, current research on ultrahigh data-rate mm-wave communication systems (e.g., 100 Gbit/s wireless communication) focuses on increasing the symbol rate while keeping the modulation format simple (e.g., quadrature phase shift keying). These systems require data converters with nominal bit resolutions of around 4-8 bit and sample rates of more than 25 GS/s. In order to satisfy the future needs for high-speed data converters, new circuit topologies need to be investigated. This work presents the design of a 35.84-GS/s 4-bit analog-to-digital converter (ADC) from its idea to its first silicon implementation. The ADC is based on a single-core flash architecture that makes use of a special traveling-wave signal distribution. Contrary to classical approaches with a power-hungry and area-consuming front-end track-and-hold (T/H), no analog preprocessing is needed. The analog input and the clock signal are rather directly distributed over a pair of delay-matched transmission lines from one comparator to the next adjacent one. Due the spatial location of these components, both signals do not arrive at the same time at every comparator, but as they travel synchronously along the transmission lines, each comparator will always see the same input value at each sampling event. This work gives detailed insight into critical design aspects of this approach and new mathematical models to predict the impact of data-to-clock time skews onto the converter linearity. Furthermore, essential building components (e.g., linear amplifiers, encoder, etc.) and a real-time digital communication interface for multi-gigabit/s data transmission to external devices are presented. The ADC is implemented in a 130-nm SiGe BiCMOS technology from IHP (SG13G2) and exhibits a die area of 1.3 mm^2. For experimental tests, the ADC is wire-bonded on a specially designed radio frequency (RF) printed circuit board. At a sampling rate of 35.84 GS/s, the peak spurious-free dynamic range (SFDR) is 35.4 dBc and the peak signal-to-noise-and-distortion ratio (SNDR) is 24.6 dB (3.8 bit). The effective resolution bandwidth (ERBW) is 14.52 GHz and covers almost the complete first Nyquist frequency band. Up to input frequencies of 20 GHz, a SFDR of more than 26.7 dBc and a SNDR of more than 19.8 dB (3 bit) is achieved. Even at a sample rate of 40.32 GS/s, full Nyquist performance can be demonstrated (SNDR = 18.4 dB @20 GHz). The presented ADC improves the sample rate of current state-of-the-art single-core ADCs by 61% from 25 GS/s to 40 GS/s, making it not only the smallest, but also the fastest reported single-core implementation up to date.Item Open Access A comparison of system architectures for wireless links in the terahertz band(2022) Dan, Iulia; Kallfass, Ingmar (Prof. Dr.-Ing.)This thesis shows an in-depth analysis of two system architecures used for future terahertz communication systems. For each architecture wireless data transmissions are carried out based on analog frontend devices that use that particular architecuture. The performance of the links is compared and the structure of the wireless links is described in detail and analyzed.Item Open Access Driver alertness monitoring using steering, lane keeping and eye tracking data under real driving conditions(2020) Friedrichs, Fabian; Yang, Bin (Prof. Dr.-Ing.)Since humans operate trains, vehicles, aircrafts and industrial machinery, fatigue has always been one of the major causes of accidents. Experts assert that sleepiness is among the major causes of severe road accidents. In-vehicle fatigue detection has been a research topic since the early 80’s. Most approaches are based on driving simulator studies, but do not properly work under real driving conditions. The Mercedes-Benz ATTENTION ASSIST is the first highly sophisticated series equipment driver assistance system on the market that detects early signs of fatigue. Seven years of research and development with an unparalleled demand of resources were necessary for its series introduction in 2009 for passenger cars and 2012 for busses. The system analyzes the driving behavior and issues a warning to sleepy drivers. Essentially, this system extracts a single measure (so-called feature), the steering event rate by detecting a characteristic pattern in the steering wheel angle signal. This pattern is principally described by a steering pause followed by a sudden correction. Various challenges had to be tackled for the series-production readiness, such as handling individual driving styles and external influences from the road, traffic and weather. Fuzzy logic, driving style detection, road condition detection, change of driver detection, fixed-point parameter optimization and sensor surveillance were some of the side results from this thesis that were essential for the system’s maturity. Simply issuing warnings to sleepy drivers is faintly "experiencable" nor transparent. Thus, the next version 2.0 of the system was the introduction of the more vivid ATTENTION LEVEL, which is a permanently available bargraph monitoring the current driving performance. The algorithm is another result of this thesis and was introduced 2013 in the new S-Class. Fatigue is very difficult to grasp since a ground truth reference does not exist. Thus, the presented findings about camera-based driver monitoring are included as fatigue reference for algorithm training. Concurrently, the presented results build the basis for eye-monitoring cameras of the future generation of such systems. The driver monitoring camera will also play a key role in "automated driving" since it is necessary to know if the driver looks to the road while the vehicle is driving and if he is alert enough to take back control over the vehicle in complex situations. All these improvements represent major steps towards the paradigm of crash free driving. In order to develop and improve the ATTENTION ASSIST, the central goal of the present work was the development of pattern detection and classification algorithms to detect fatigue from driving sensors. One major approach to achieve a sufficiently high detection rate while maintaining the false alarm rate at a minimum was the incorporation of further patterns with sleepiness-associative ability. Features reported in literature were assessed as well as improved extraction techniques. Various new features were proposed for their applicability under real-road conditions. The mentioned steering pattern detection is the most important feature and was further optimized. Essential series sensor signals, available in most today’s vehicles were considered, such as steering wheel angle, lateral and longitudinal acceleration, yaw rate, wheel rotation rate, acceleration pedal, wheel suspension level, and vehicle operation. Another focus was on the lateral control using camera-based lane data. Under real driving conditions, the effects of sleepiness on the driving performance are very small and severely obscured by external influences such as road condition, curvature, cross-wind, vehicle speed, traffic, steering parameters etc. Furthermore, drivers also have very different individual driving styles. Short-term distraction from vehicle operation also has a big impact on the driving behavior. Proposals are given on how to incorporate such factors. Since lane features require an optional tracking camera, a proposal is made on how to estimate some lane deviation features from only inertial sensory by means of an extended Kalman filter. Every feature is related to a number of parameters and implementation details. A highly accelerated method for parameter optimization of the large amount of data is presented and applied to the most promising features. The alpha-spindle rate from the Electroencephalogram (EEG) and Electrooculogram (EOG) were assessed for their performance under real driving conditions. In contrast to the majority of results in literature, EEG was not observed to contribute any useful information to the fatigue reference (except for two drives with microsleeps). Generally, the subjective self-assessments according to the Karolinska Sleepiness Scale and a three level warning acceptance question were consequently used. Various correlation measures and statistical test were used to assess the correlation of features with the reference. This thesis is based on a database with over 27,000 drives that accumulate to over 1.5 mio km of real-road drives. In addition, various supervised real-road driving studies were conducted that involve advanced fatigue levels. The fusion of features is performed by different classifiers like Artificial Neural Networks (ANN) and Support Vector Machines (SVM). Fair classification results are achieved with ANN and SVM using cross-validation. A selection of the most potential and independent features is given based on automatic SFFS feature selection. Classical machine learning methods are used in order to yield maximal system transparency and since the algorithms are targeted to run in present control units. The potential of using end-to-end deep learning algorithms is discussed. Whereas its application to CAN-signals is problematic, there is a high potential for driver-camera based approaches. Finally, features were implemented in a real-time demonstrator using an own CAN-interface framework. While various findings are already rolled out in ATTENTION ASSIST 1.0, 2.0 and ATTENTION LEVEL, it was shown that further improvements are possible by incorporating a selection of steering- and lane-based features and sophisticated classifiers. The problem can only be solved on a system level considering all topics discussed in this thesis. After decades of research, it must be recognized that the limitations of indirect methods have been reached. Especially in view of emerging automated driving, direct methods like eye-tracking must be considered and have shown the greatest potential.Item Open Access An in-cell integrated system for the real-time monitoring of Lithium-ion battery cells(2021) Saidani, Fida; Burghartz, Joachim (Prof. Dr.-Ing.)Item Open Access Dependable reconfigurable scan networks(2022) Lylina, Natalia; Wunderlich, Hans-Joachim (Prof.)The dependability of modern devices is enhanced by integrating an extensive number of extra-functional instruments. These are needed to facilitate cost-efficient bring-up, debug, test, diagnosis, and adaptivity in the field and might include, e.g., sensors, aging monitors, Logic, and Memory Built-In Self-Test (BIST) registers. Reconfigurable Scan Networks (RSNs) provide a flexible way to access such instruments as well the device's registers throughout the lifetime, starting from post-silicon validation (PSV) through manufacturing test and finally during in-field operation. At the same time, the dependability properties of the system can be affected through an improper RSN integration. This doctoral project overcomes these problems and establishes a methodology to integrate dependable RSNs for a given system considering the most relevant dependability aspects, such as robustness, testability, and security compliance of RSNs.Item Open Access Switching characteristics of integrated GaN-on-Si half-bridge and driver circuits(2021) Mönch, Stefan; Kallfass, Ingmar (Prof. Dr.-Ing.)This work examines particularities in the switching characteristics of gallium nitride (GaN) half-bridge and driver circuits, which arise from the integration on a common conductive silicon (Si) substrate, or from the operation of discrete devices on an electrically coupled Si substrate. The supposed advantages of monolithic integrated half-bridges and drivers are promising: The reduced parasitic interconnect inductance improves voltage-switching transitions. The Si carrier allows low-cost and large-scale fabrication. A single integrated IC simplifies the assembly compared to conventional multi-chip power modules. However, the operation of such monolithic GaN-on-Si power circuits also evokes substrate-related effects, especially at elevated operation voltages, which were previously not relevant for single low-side GaN HEMTs. On the one hand, deteriorating effects such as on-resistance increase by negative substrate biasing (back-gating) have to be considered. On the other hand, beneficial effects such as the possibility of decoupling of substrate capacitances can be exploited for reduction of switching energies and consequently increased efficiencies compared to conventional discrete GaN power transistors. Furthermore, even though the monolithic integration of a gate driver with a power transistor reduces the interconnect parasitics between the driver and the transistor, still external interconnects to decoupling capacitors are required. The monolithic integration of half-bridges and drivers thus does not fully eliminate parasitic gate-loop and power-loop inductance. Therefore, advanced assembly technologies such as PCB-embedding of GaN-based power integrated circuits should also be considered in combination with the monolithic circuit integration. First, this work provides a theoretical framework to calculate and compare the effect of substrate-capacitances on application-oriented half-bridge capacitances for different feasible substrate terminations of discrete and monolithic GaN-on-Si half-bridges. It is explained and verified how floating substrate terminations reduce the effective output capacitances. To harness the benefits of this reduced effective capacitances, an improved passive substrate biasing network for monolithic half-bridges is proposed and experimentally verified: The proposed operation scheme for monolithic half-bridges avoids negative back-gating in all operation points of a dc-dc converter and at the same time has reduced effective output capacitance compared to a discrete half-bridge. Experimental operation of a monolithic half-bridge with the proposed substrate biasing network shows increased efficiency compared to a discrete half-bridge and verifies the effectiveness of the proposed duty-cycle independent floating substrate biasing. Compared to a conventional discrete half-bridge with two substrate-to-source terminated transistors, this work's operation scheme for a monolithic half-bridge in a dc-dc converter with 200 V input voltage, 100 V output voltage, 1.5 A load current and 100 kHz switching frequency, reduced the switching energies by over 20%, and the total power loss in a dc-dc converter by over 10%. This efficiency improvement is the results of this work's beneficial combination of a (semi-)floating substrate which reduces the effective output capacitance, and the novel substrate biasing network which avoids negative back-gating during conduction phases by shifting the average substrate voltage towards higher values. Then, this work work analyzes high slew-rate voltage switching transitions and the effect of parasitic inductance in the power-loop on switch-node overshoot voltage. An equivalent circuit analysis is carried out, which takes the limited voltage slew-rate of a power transistor into account. In contrast to a simplified RLC-circuit analysis with a infinitely fast voltage excitation pulse, this work analytically provides insight into the dependency of switch-node overshoot voltage on the voltage transition time. Even though the power-loop is almost undamped due to the low on-resistance of the transistors, the analysis shows that local minima of overshoot as a function of switching time exist, and by selection of optimal switching times it is possible to minimize the overshoot without a significant reduction of switching speed. Furthermore, an advanced PCB-embedded packaging technology is combined with on-package gate and dc-link capacitors, which further reduces parasitic inductance of GaN half-bridges with integrated drivers. Finally, this work exposes that the substrate-to-source termination of a lateral GaN power transistor, which is typically realized on the packaging level, forms a third parasitic loop. In addition to the well-known parasitic gate-loop and power-loop inductance, this work analyzes the effects of this substrate-loop inductance. An analytical and experimental stability analysis is carried out. Countermeasures are proposed to avoid instabilities from the parasitic-substrate loop. A substrate damping circuit is proposed, which avoids instabilities by damping of the substrate-loop, without slowing down of the switching transition. The experimental and theoretical investigation and results of this work on the switching characteristic of GaN-on-Si half-bridges with drivers on conductive Si substrates contributes to unlock the benefits of GaN HEMTs and monolithic power circuit integration for compact, clean switching and highly efficient power electronics.