05 Fakultät Informatik, Elektrotechnik und Informationstechnik
Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6
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Item Open Access Efficient fault tolerance for selected scientific computing algorithms on heterogeneous and approximate computer architectures(2018) Schöll, Alexander; Wunderlich, Hans-Joachim (Prof. Dr.)Scientific computing and simulation technology play an essential role to solve central challenges in science and engineering. The high computational power of heterogeneous computer architectures allows to accelerate applications in these domains, which are often dominated by compute-intensive mathematical tasks. Scientific, economic and political decision processes increasingly rely on such applications and therefore induce a strong demand to compute correct and trustworthy results. However, the continued semiconductor technology scaling increasingly imposes serious threats to the reliability and efficiency of upcoming devices. Different reliability threats can cause crashes or erroneous results without indication. Software-based fault tolerance techniques can protect algorithmic tasks by adding appropriate operations to detect and correct errors at runtime. Major challenges are induced by the runtime overhead of such operations and by rounding errors in floating-point arithmetic that can cause false positives. The end of Dennard scaling induces central challenges to further increase the compute efficiency between semiconductor technology generations. Approximate computing exploits the inherent error resilience of different applications to achieve efficiency gains with respect to, for instance, power, energy, and execution times. However, scientific applications often induce strict accuracy requirements which require careful utilization of approximation techniques. This thesis provides fault tolerance and approximate computing methods that enable the reliable and efficient execution of linear algebra operations and Conjugate Gradient solvers using heterogeneous and approximate computer architectures. The presented fault tolerance techniques detect and correct errors at runtime with low runtime overhead and high error coverage. At the same time, these fault tolerance techniques are exploited to enable the execution of the Conjugate Gradient solvers on approximate hardware by monitoring the underlying error resilience while adjusting the approximation error accordingly. Besides, parameter evaluation and estimation methods are presented that determine the computational efficiency of application executions on approximate hardware. An extensive experimental evaluation shows the efficiency and efficacy of the presented methods with respect to the runtime overhead to detect and correct errors, the error coverage as well as the achieved energy reduction in executing the Conjugate Gradient solvers on approximate hardware.Item Open Access Fault emulation for reconfigurable scan networks(2018) Schwachhofer, DenisAt around their standardization by the IEEE the interest on Reconfigurable Scan Networks (RSNs) by research and industry sparked. The testing of RSNs also raises new challenges. To analyze and cope with these challenges researchers are required to perform fault simulation. And the industry incorporated RSNs into their designs and need to test them to which also requires fault simulation. But the runtime of it is significantly high due to the RSNs’ structure. This thesis introduces a platform for fault emulation of RSNs and analyzes its feasibility. The speedup compared to fault simulation is presented and advantages, limitations and possible optimizations are evaluated and discussed.Item Open Access Improvement of hardware reliability with aging monitors(2017) Liu, Chang; Wunderlich, Hans-Joachim (Prof. Dr.)Item Open Access Software-basierter Selbsttest von Peripherie-Komponenten(2015) Bäßler, JochenSoftware-basierte Selbsttest (SBST) Verfahren werden zumeist für das Testen von Mikroprozessoren eingesetzt, lassen sich jedoch auch auf Peripheriekomponenten anwenden. Der Vorteil von SBST, gegenüber Hardware-basierten Ansätzen besteht dabei im Verzicht auf spezielle Testhardware und Hochgeschwindigkeitstestgeräte und der Tatsache, dass Tests in der natürlichen Betriebsumgebung (engl. In-System) und bei normaler Betriebsfrequenz (engl. At-Speed) ablaufen. Peripheriekomponenten nehmen in vielen Systemen einen erheblichen Teil der Chipfläche ein, werden teilweise für sicherheitskritische Aufgaben eingesetzt und müssen folglich ausgiebig getestet werden. Um strukturelle SBST-Verfahren erfolgreich auf diesen Typ von Komponenten anzuwenden, müssen Maßnahmen getroffen werden um deren geringe Beobacht- und Kontrollierbarkeit zu erhöhen, da andernfalls die erzielte Fehlerabdeckung der Verfahren zu niedrig ausfällt. In dieser Arbeit werden zwei unterschiedliche Ansätze untersucht, um die strukturelle Fehlerabdeckung von SBST-Verfahren auf Kommunikationsperipheriekomponenten zu verbessern. Der erste Ansatz zielt auf eine verbesserte Kontrollierbarkeit der verwendeten Komponente ab. Dazu wird ein Loopback-basierter Mechanismus implementiert. Um darüber hinaus eine bessere Beobachtbarkeit zu erreichen wird als zweiter Ansatz der Zustand ausgewählter internen Signale dem System sichtbar gemacht. Eine beispielhafte Anwendung der vorgestellten Methode auf die I2C-Komponente eines RISC-Prozessors zeigt die Wirksamkeit der verwendeten Maßnahmen zur Verbesserung der strukturellen Fehlerabdeckung.Item Open Access Adaptierung an Zeitverhalten-Variationen in rekonfigurierbaren Hardwarestrukturen(2015) Brandhofer, SebastianDas Zeitverhalten von Komponenten in rekonfigurierbaren Hardwarestrukturen kann durch Alterungseffekte und zufällige Defekte variieren. Wenn ein System nicht an diese Abweichungen vom nominellen Zeitverhalten adaptiert werden kann, entstehen Verzögerungsfehler während des Betriebs, die zu falschen Ergebnissen oder Systemausfällen führen können. Insbesondere in sicherheitskritischen Anwendungen von rekonfigurierbaren Hardwarestrukturen kann dies zu Gefährdung von Personen führen. Diese Arbeit stellt einen Algorithmus zur Adaptierung an Zeitverhalten-Variationen in rekonfigurierbaren Hardwarestrukturen vor, der Alterung von Komponenten sowie zufällige Defekte berücksichtigt und Verzögerungsfehler durch eine dem Zeitverhalten angepasste Nutzung der rekonfigurierbaren Hardwarestrukturen vermeidet. Der entworfene Algorithmus wird mit Hilfe von verschiedenen Verzögerungsverteilungen hinsichtlich der Adaptionsfähigkeit, Speicheranforderungen und Laufzeit untersucht.Item Open Access Software-basierter Selbsttest eingebetteter Speicher(2015) Ebinger, FelixProzessoren werden häufig mittels softwarebasierter Selbsttests (SBST) getestet, da dieses Testverfahren mehrere Vorteile besitzt. Zunächst ist der Test zerstörungsfrei, und wird im funktionalen Betriebszustand des Prozessors durchgeführt. Es ist weder eine Veränderung des Hardwaredesigns erforderlich noch ist ein Übertesten möglich. Die Testmethode ist flexibel einsetzbar und kann sowohl beim Herstellungstest als auch im Feld genutzt werden. Speicher werden dagegen üblicherweise mittels eingebauter Selbsttests (engl. built-in self-test, BIST) getestet, da der Overhead durch die zusätzliche Testhardware nur gering ausfällt und diese Tests bei Speichern ohne Performance-Einbußen realisiert werden können. In dieser Arbeit wird die softwarebasierte Umsetzung von Speichertests untersucht um die Vorteile softwarebasierter Selbsttests auch bei Speichertests nutzen zu können. Dies stellt eine Herausforderung dar, da softwarebasiert nicht jede Operationsfolge mit frei wählbarem Zeitverhalten erzeugt werden kann. Insbesondere bei dynamischen Fehlern kann dies zu einer Verringerung der Testabdeckung führen. Hierzu wird ein Framework zur automatischen Umwandlung von Marchtestbeschreibungen in Testprogramme für den miniMIPS-Prozessor vorgestellt. Dabei steht besonders die Laufzeit des Testprogramms und die erreichte Testabdeckung im Vordergrund. Die Testabdeckung wird durch Simulation und Fehlerinjektion experimentell bestimmt. Es zeigt sich, dass die Fehlerabdeckung für die untersuchten statische und dynamische Fehlermodelle durch die vorgestellte Implementierung in Software nicht beeinträchtigt wird.Item Open Access Realistic gate model for efficient timing analysis of very deep submicron CMOS circuits(2016) Murali, DeepthiThe continuously shrinking technology has made it possible for designers to incorporate more functionality with better performance at a much higher density in Integrated Circuits (ICs). Fast and accurate timing simulation of such large circuit designs using ever more complex transistor models has become a challenging problem. In modern circuits, the gate delay is severely affected by process variations, environmental variations and cross talk. Moreover, technology scaling has also resulted in significant increase in interconnect parasitics (including resistors and capacitors) which can dramatically reduce the performance of a circuit. For the circuit design validation and delay test evaluation, the industry has long relied on fast gate-level timing simulators like ModelSim to validate the designs. However, with continued scaling and steadily increasing circuit performance requirements, gate level simulators can no longer provide acceptable simulation accuracy. On the other hand, circuit level SPICE simulation provides acceptable accuracy but at a very large computational cost. To provide a suitable trade-off between the accuracy of the SPICE simulation and the speed of the gate level simulation, this thesis proposes a realistic gate model which can be used for the fast and accurate timing simulation of circuits to analyze their timing behaviour. In this thesis, a heterogeneous gate model that combines a simple gate model like Non-Linear Delay Model (NLDMs) and an advanced current source model (CSM) using a classifier is proposed. The simple gate model allows fast timing simulation and gives acceptable accuracy in many cases while the advanced gate model always provides more accurate and reliable results, but at a much higher computational cost. The classifier is designed to choose the advanced gate model depending on special cases (eg, multiple input switching) where the simple gate model gives inappropriate results. This heterogeneous gate model is further applied to develop a circuit simulator that enables fast and accurate post-layout and delay fault simulation.Item Open Access Machine learning support for logic diagnosis(2017) Rodríguez Gómez, Laura; Wunderlich, Hans-Joachim (Prof. Dr.)Item Open Access Self-diagnosis in Network-on-Chips(2015) Dalirsani, Atefe; Wunderlich, Hans-Joachim (Dr. rer. nat. habil.)Network-on-Chips (NoCs) constitute a message-passing infrastructure and can fulfil communication requirements of the today’s System-on-Chips (SoCs), which integrate numerous semiconductor Intellectual Property (IP) blocks into a single die. As the NoC is responsible for data transport among IPs, its reliability is very important regarding the reliability of the entire system. In deep nanoscale technologies, transient and permanent failures of transistors and wires are caused by variety of effects. Such failures may occur in the NoC as well, disrupting its normal operation. An NoC comprises a large number of switches that form a structure spanning across the chip. Inherent redundancy of the NoC provides multiple paths for communication among IPs. Graceful degradation is the property of tolerating a component’s failure in a system at the cost of limited functionality or performance. In NoCs, when a switch in the path is faulty, alternative paths can be used to connect IPs, keeping the SoC functional. To this purpose, a fault detection mechanism is needed to identify the faulty switch and a fault tolerant routing should bypass it. As each NoC switch consists of a number of ports and multiple routing paths, graceful degradation can be considered even in a rather granular way. The fault may destroy some routing paths inside the switch, leaving the rest non-faulty. Thus, instead of disabling the faulty switch completely, its fault-free parts can be used for message passing. In this way, the chance of disconnecting the IP cores is reduced and the probability of having disjoint networks decreases. This study pursues efficient self-test and diagnosis approaches for both manufacturing and in-field testing aiming at graceful degradation of defective NoCs. The approaches here identify the location of defective components in the network rather than providing only a go/no-go test response. Conventionally, structural test approaches like scan-design have been employed for testing the NoC products. Structural testing targets faults of a predefined structural fault model like stuck-at faults. In contrast, functional testing targets certain functionalities of a system for example the instructions of a microprocessor. In NoCs, functional tests target NoC characteristics such as routing functions and undistorted data transport. Functional tests get the highest gain of the regular NoC structure. They reduce the test costs and prevent overtesting. However, unlike structural tests, functional tests do not explicitly target structural faults and the quality of the test approach cannot be measured. We bridge this gap by proposing a self-test approach that combines the advantages of structural and functional test methodologies and hence is suitable for both manufacturing and in-field testing. Here, the software running on the IP cores attached to the NoC is responsible for test. Similar to functional tests, the test patterns here deal only with the functional inputs and outputs of switches. For pattern generation, a model is introduced that brings the information about structural faults to the level of functional outputs of the switch. Thanks to this unique feature of the model, a high structural fault coverage is achieved as revealed by the results. To make NoCs more robust against various defect mechanisms during the lifetime, concurrent error detection is necessary. Toward this, this dissertation contributes an area efficient synthesis technique of NoC switches to detect any error resulting from single combinational and transition fault in the switch and its links during the normal operation. This technique incorporates data encoding and the standard concurrent error detection using multiple parity trees. Results reveal that the proposed approach imposes less area overhead as compared to traditional techniques for concurrent error detection. To enable fine-grained graceful degradation, intact functions of defective switches must be identified. Thanks to the fault tolerant techniques, fault-free parts of switches can be still employed in the NoC. However, reasoning about the fault-free functions with respect to the exact cause of a malfunction is missing in the literature. This dissertation contributes a novel fine-grained switch diagnosis technique that works based on the structural logic diagnosis. After determining the location and the nature of the defect in the faulty switch, all routing paths are checked and the soundness of the intact switch functions is proved. Experimental results show improvements in both performance and reliability of degraded NoCs by incorporating the fine-grained diagnosis of NoC switches.Item Open Access Algorithm-based fault tolerance for matrix operations on graphics processing units : analysis and extension to autonomous operation(2015) Braun, Claus; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat. habil.)Scientific computing and computer-based simulation technology evolved to indispensable tools that enable solutions for major challenges in science and engineering. Applications in these domains are often dominated by compute-intensive mathematical tasks like linear algebra matrix operations. The provision of correct and trustworthy computational results is an essential prerequisite since these applications can have direct impact on scientific, economic or political processes and decisions. Graphics processing units (GPUs) are highly parallel many-core processor architectures that deliver tremendous floating-point compute performance at very low cost. This makes them particularly interesting for the substantial acceleration of complex applications in science and engineering. However, like most nano-scaled CMOS devices, GPUs are facing a growing number of threats that jeopardize their reliability. This makes the integration of fault tolerance measures mandatory. Algorithm-Based Fault Tolerance (ABFT) allows the protection of essential mathematical operations, which are intensively used in scientific computing. It provides a high error coverage combined with a low computational overhead. However, the integration of ABFT into linear algebra matrix operations on GPUs is a non-trivial task, which requires a thorough balance between fault tolerance, architectural constraints and performance. Moreover, ABFT for operations carried out in floating-point arithmetic has to cope with a reduced error detection and localization efficacy due to inevitable rounding errors. This work provides an in-depth analysis of Algorithm-Based Fault Tolerance for matrix operations on graphics processing units with respect to different types and combinations of weighted checksum codes, partitioned encoding schemes and architecture-related execution parameters. Moreover, a novel approach called A-ABFT is introduced for the efficient online determination of rounding error bounds, which improves the error detection and localization capabilities of ABFT significantly. Extensive experimental evaluations of the error detection capabilities, the quality of the determined rounding error bounds, as well as the achievable performance confirm that the proposed A-ABFT method performs better than previous approaches. In addition, two case studies (QR decomposition and Linear Programming) emphasize the efficacy of A-ABFT and its applicability to practical problems.