05 Fakultät Informatik, Elektrotechnik und Informationstechnik
Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6
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Item Open Access Interacting with large high-resolution display workplaces(2018) Lischke, Lars; Schmidt, Albrecht (Prof.)Large visual spaces provide a unique opportunity to communicate large and complex pieces of information; hence, they have been used for hundreds of years for varied content including maps, public notifications and artwork. Understanding and evaluating complex information will become a fundamental part of any office work. Large high-resolution displays (LHRDs) have the potential to further enhance the traditional advantages of large visual spaces and combine them with modern computing technology, thus becoming an essential tool for understanding and communicating data in future office environments. For successful deployment of LHRDs in office environments, well-suited interaction concepts are required. In this thesis, we build an understanding of how concepts for interaction with LHRDs in office environments could be designed. From the human-computer interaction (HCI) perspective three aspects are fundamental: (1) The way humans perceive and react to large visual spaces is essential for interaction with content displayed on LHRDs. (2) LHRDs require adequate input techniques. (3) The actual content requires well-designed graphical user interfaces (GUIs) and suitable input techniques. Perceptions influence how users can perform input on LHRD setups, which sets boundaries for the design of GUIs for LHRDs. Furthermore, the input technique has to be reflected in the design of the GUI. To understand how humans perceive and react to large visual information on LHRDs, we have focused on the influence of visual resolution and physical space. We show that increased visual resolution has an effect on the perceived media quality and the perceived effort and that humans can overview large visual spaces without being overwhelmed. When the display is wider than 2 m users perceive higher physical effort. When multiple users share an LHRD, they change their movement behavior depending whether a task is collaborative or competitive. For building LHRDs consideration must be given to the increased complexity of higher resolutions and physically large displays. Lower screen resolutions provide enough display quality to work efficiently, while larger physical spaces enable users to overview more content without being overwhelmed. To enhance user input on LHRDs in order to interact with large information pieces, we built working prototypes and analyzed their performance in controlled lab studies. We showed that eye-tracking based manual and gaze input cascaded (MAGIC) pointing can enhance target pointing to distant targets. MAGIC pointing is particularly beneficial when the interaction involves visual searches between pointing to targets. We contributed two gesture sets for mid-air interaction with window managers on LHRDs and found that gesture elicitation for an LHRD was not affected by legacy bias. We compared shared user input on an LHRD with personal tablets, which also functioned as a private working space, to collaborative data exploration using one input device together for interacting with an LHRD. The results showed that input with personal tablets lowered the perceived workload. Finally, we showed that variable movement resistance feedback enhanced one-dimensional data input when no visual input feedback was provided. We concluded that context-aware input techniques enhance the interaction with content displayed on an LHRD so it is essential to provide focus for the visual content and guidance for the user while performing input. To understand user expectations of working with LHRDs we prototyped with potential users how an LHRD work environment could be designed focusing on the physical screen alignment and the placement of content on the display. Based on previous work, we implemented novel alignment techniques for window management on LHRDs and compared them in a user study. The results show that users prefer techniques, that enhance the interaction without breaking well-known desktop GUI concepts. Finally, we provided the example of how an application for browsing scientific publications can benefit from extended display space. Overall, we show that GUIs for LHRDs should support the user more strongly than GUIs for smaller displays to arrange content meaningful or manage and understand large data sets, without breaking well-known GUI-metaphors. In conclusion, this thesis adopts a holistic approach to interaction with LHRDs in office environments. Based on enhanced knowledge about user perception of large visual spaces, we discuss novel input techniques for advanced user input on LHRDs. Furthermore, we present guidelines for designing future GUIs for LHRDs. Our work creates the design space of LHRD workplaces and identifies challenges and opportunities for the development of future office environments.Item Open Access Efficient fault tolerance for selected scientific computing algorithms on heterogeneous and approximate computer architectures(2018) Schöll, Alexander; Wunderlich, Hans-Joachim (Prof. Dr.)Scientific computing and simulation technology play an essential role to solve central challenges in science and engineering. The high computational power of heterogeneous computer architectures allows to accelerate applications in these domains, which are often dominated by compute-intensive mathematical tasks. Scientific, economic and political decision processes increasingly rely on such applications and therefore induce a strong demand to compute correct and trustworthy results. However, the continued semiconductor technology scaling increasingly imposes serious threats to the reliability and efficiency of upcoming devices. Different reliability threats can cause crashes or erroneous results without indication. Software-based fault tolerance techniques can protect algorithmic tasks by adding appropriate operations to detect and correct errors at runtime. Major challenges are induced by the runtime overhead of such operations and by rounding errors in floating-point arithmetic that can cause false positives. The end of Dennard scaling induces central challenges to further increase the compute efficiency between semiconductor technology generations. Approximate computing exploits the inherent error resilience of different applications to achieve efficiency gains with respect to, for instance, power, energy, and execution times. However, scientific applications often induce strict accuracy requirements which require careful utilization of approximation techniques. This thesis provides fault tolerance and approximate computing methods that enable the reliable and efficient execution of linear algebra operations and Conjugate Gradient solvers using heterogeneous and approximate computer architectures. The presented fault tolerance techniques detect and correct errors at runtime with low runtime overhead and high error coverage. At the same time, these fault tolerance techniques are exploited to enable the execution of the Conjugate Gradient solvers on approximate hardware by monitoring the underlying error resilience while adjusting the approximation error accordingly. Besides, parameter evaluation and estimation methods are presented that determine the computational efficiency of application executions on approximate hardware. An extensive experimental evaluation shows the efficiency and efficacy of the presented methods with respect to the runtime overhead to detect and correct errors, the error coverage as well as the achieved energy reduction in executing the Conjugate Gradient solvers on approximate hardware.Item Open Access Computational modelling of coreference and bridging resolution(2019) Rösiger, Ina; Kuhn, Jonas (Prof. Dr.)Item Open Access Organische Dünnschichttransistoren mit gedrucktem Halbleiter für Schaltungen und Anzeigen(2019) Strecker, Michael; Frühauf, Norbert (Prof. Dr.-Ing.)Die vorliegende Arbeit behandelt die Entwicklung von organischen Dünnschichttransistoren mit gedrucktem Halbleiter für Anwendungen der gedruckten Elektronik. Der Schwerpunkt liegt dabei auf der Untersuchung der Abscheidung organischer Halbleiterlösungen durch Tintenstrahldruck, während die Abscheidung und Strukturierung der übrigen Metallisierungen auf vorwiegend konventionellen Dünnschichtprozessen basieren. Entsprechend potentieller Einsatzmöglichkeiten gedruckter Elektronik wurde die Entwicklung an einen energiesparenden Betrieb ausgerichtet. Als Halbleiter wurden daher Lösungen aus einem Polymer (p-Typ) und einem Perylendiimid-Derivat (PDI, nTyp) eingesetzt, mit dem Ziel eines kompatiblen Prozesses zum Einsatz der Transistoren in komplementären Ansteuerschaltungen und Anzeigen. Ein niedriges Spannungsniveau wurde durch ein dünnes, anodisiertes Dielektrikum mit hohem Kapazitätsbelag realisiert. Die Halbleiter wurden vor allem hinsichtlich ihrer Verdruckbarkeit, der morphologischen Eigenschaften und des daraus resultierenden elektrischen Verhaltens der Transistoren untersucht. Eine zentrale Erkenntnis ist, dass die Halbleiter sich aufgrund ihrer unterschiedlichen Stoffeigenschaften in der Verarbeitbarkeit durch den Druckprozess erheblich unterscheiden. Der Polymerhalbleiter zeichnet sich durch ein im Wesentlichen unproblematisches Benetzungsverhalten, robuste Prozessierbarkeit und vergleichsweise geringe Ladungsträgerbeweglichkeit µ ≈10−3cm2V−1s−1 aus. Dagegen sind das Benetzungsverhalten und die Morphologie des PDI-Derivats stark vom gewählten Lösemittel abhängig. Die Morphologie variiert von körnigen, diskontinuierlichen Filmen mit amorpher Struktur (o-DCB, Tetralin) bis hin zu ebenen, polykristallinen Filmen (Dimethylphthalat, DMP). Entsprechend variiert die erzielte Ladungsträgerbeweglichkeit typischerweise von µ≈10−4cm2V−1s−1 bis µ≈10−1cm2V−1s−1. In allen Fällen zeichnet sich der Nassfilm durch eine ausgeprägte Spreitung aus. Während die Trocknung bei Lösungen aus o-DCB und Tetralin innerhalb weniger Sekunden abgeschlossen ist, dauert dies bei DMP aufgrund des niedrigen Dampfdrucks mehrere Minuten. Die endgültige Lage des Halbleiters kann dabei weder vorhergesagt noch kontrolliert werden, da es während der Trocknung zur willkürlichen Wanderung des Nassfilms relativ zu den bedruckten Transistorstrukturen kommt. Daher waren technologische Maßnahmen erforderlich, um die Lokalisation des Halbleiters reproduzierbar sicherzustellen. Hierzu wurden zwei Ansätze untersucht. Einerseits erfolgte die Lokalisation durch lokal modulierte Oberflächenspannungen mithilfe von strukturierten, selbstorganisierenden Monolagen mit hydrophobem Charakter. Dieser Prozess eignet sich auch zur Lokalisierung des Polymerhalbleiters, falls eine erhöhte Integrationsdichte erforderlich ist. Für das PDI-Derivat hat sich die Lokalisierung durch strukturierte Polymerwannen als Prozess der Wahl herausgestellt. Obwohl die Halbleiter, insbesondere das PDI-Derivat, bereits an Luft eine hohe Umweltstabilität aufweisen, wurde die Verkapselung der Halbleiter untersucht. Eine Verkapselung ist unabhängig von der intrinsischen Stabilität in komplexen, mehrschichtigen Systemen, wie Schaltungen und Anzeigen, erforderlich, um den Halbleiter vor nachfolgenden Prozessschritten zu schützen. Als Material der Wahl hat sich ein fluorierter Photolack basierend auf gegenüber den Halbleitern orthogonalen Lösemitteln erwiesen. Insbesondere der Polymerhalbleiter zeigt durch die Verkapselung eine Stabilisierung der Schwellspannung und eine erhöhte Langzeitstabilität. Durch die hydrophobe Verkapselung bleibt sogar eine mehrstündige Immersion in Wasser ohne Auswirkungen auf das Verhalten der Transistoren. Für beide Halbleitertypen wurden jeweils Prozesse für ein optimales Betriebsverhalten entwickelt. Aufgrund technologischer Einschränkungen und der geforderten ähnlichen Eigenschaften der Transistoren in komplementären Schaltungen ist die Schnittmenge eines für beide Halbleitertypen kompatiblen Prozesses allerdings gering. Die Realisierung komplementärer Grundschaltungen erfolgte daher auf Basis des BGBC-Prozesses mit Abscheidung des PDI-Derivats aus o-DCB. Die hergestellten Inverter, Nand-Gatter und Ringoszillatoren waren funktionsfähig, allerdings stellte sich die Betriebsstabilität als problematisch heraus. Durch elektrische Beanspruchung trat eine signifikante Verschiebung der Schwellspannungen ein, was zur raschen Degradation der Signalpegel führte. Alternativ wurde die unipolare Pseudo-CMOS-Technik auf Basis des Polymerhalbleiters untersucht. Diese Schaltungstechnik stellte sich als wesentlich robuster heraus. Es wurde sogar eine Art Lerneffekt beobachtet, der dazu führt, dass sich das anfänglich nicht-ideale Schaltverhalten von Invertern während des Betriebs durch Angleichung der Schwellspannungen einzelner Transistoren verbessert. Die Integrierbarkeit der entwickelten Transistorprozesse in ein komplexes, mehrschichtiges System wurde durch eine funktionsfähige, elektrophoretische Aktiv-Matrix-Anzeige demonstriert. Die Anzeige hat eine Auflösung von 32×32 Bildpunkten mit Ansteuerung durch organische Transistoren mit Polymerhalbleiter. Die Lokalisation des Halbleiters wurde aufgrund der geringen Transistordimensionen erfolgreich durch selbstorganisierende Monolagen realisiert. Durch die Verkapselung hatten nachfolgende Passivierungs-, Abscheide- und Strukturierungsprozesse keine signifikanten Auswirkungen auf die Transistoren. Die maximale Temperatur bei der Prozessierung betrug 150◦C.Item Open Access Frequency-agile bandpass delta-sigma modulator for microwave transmitters(2019) Schmidt, Martin; Berroth, Manfred (Prof. Dr.-Ing.)A large part of the power consumption for mobile communications can be allotted to power amplifiers. Class-S power amplifiers promise a very high power efficiency, especially for modern communication standards. An important part of the Class-S power amplifier is the modulator that converts the input signal into a binary pulse sequence. A switching-mode power amplifier can amplify this sequence efficiently. This work covers the implementation of such a modulator as a bandpass delta-sigma modulator. The goal is an output signal which fulfills the requirements of the mobile communication standard UMTS (Universal Mobile Telecommunications System) in a frequency range which is as large as possible. The thesis starts with the basics of mobile communications, with power amplifiers and with the requirements for the transmit signals for UMTS. Based on a discrete-time lowpass delta-sigma modulator, a continuous-time bandpass delta-sigma modulator is derived. Due to project constraints a bipolar technology is selected for the implementation. Current-mode logic is used for amplifiers and latches in the digital part. Different circuits for a transconductance amplifier are derived and evaluated. A novel, switchable capacitance is presented. With the switchable capacitance a large frequency range of the modulator becomes possible. Two modulators are designed. The first modulator is not tunable and fulfills the UMTS requirements for the downlink channel from the base station to the user equipment at a signal frequency of 2.2 GHz. The second modulator uses the switchable capacitance and covers a frequency range between 1.55 GHz and 2.45 GHz. It fulfills the UMTS requirements within the frequency range between 1.8 GHz and 2.45 GHz.Item Open Access Efficient modeling and computation methods for robust AMS system design(2018) Gil, Leandro; Radetzki, Martin (Prof. Dr.-Ing.)This dissertation copes with the challenge regarding the development of model based design tools that better support the mixed analog and digital parts design of embedded systems. It focuses on the conception of efficient modeling and simulation methods that adequately support emerging system level design methodologies. Starting with a deep analysis of the design activities, many weak points of today’s system level design tools were captured. After considering the modeling and simulation of power electronic circuits for designing low energy embedded systems, a novel signal model that efficiently captures the dynamic behavior of analog and digital circuits is proposed and utilized for the development of computation methods that enable the fast and accurate system level simulation of AMS systems. In order to support a stepwise system design refinement which is based on the essential system properties, behavior computation methods for linear and nonlinear analog circuits based on the novel signal model are presented and compared regarding the performance, accuracy and stability with existing numerical and analytical methods for circuit simulation. The novel signal model in combination with the method proposed to efficiently cope with the interaction of analog and digital circuits as well as the new method for digital circuit simulation are the key contributions of this dissertation because they allow the concurrent state and event based simulation of analog and digital circuits. Using a synchronous data flow model of computation for scheduling the execution of the analog and digital model parts, very fast AMS system simulations are carried out. As the best behavior abstraction for analog and digital circuits may be selected without the need of changing component interfaces, the implementation, validation and verification of AMS systems take advantage of the novel mixed signal representation. Changes on the modeling abstraction level do not affect the experiment setup. The second part of this work deals with the robust design of AMS systems and its verification. After defining a mixed sensitivity based robustness evaluation index for AMS control systems, a general robust design method leading to optimal controller tuning is presented. To avoid over-conservative AMS system designs, the proposed robust design optimization method considers parametric uncertainty and nonlinear model characteristics. The system properties in the frequency domain needed to evaluate the system robustness during parameter optimization are obtained from the proposed signal model. Further advantages of the presented signal model for the computation of control system performance evaluation indexes in the time domain are also investigated in combination with range arithmetic. A novel approach for capturing parameter correlations in range arithmetic based circuit behavior computation is proposed as a step towards a holistic modeling method for the robust design of AMS systems. The several modeling and computation methods proposed to improve the support of design methodologies and tools for AMS system are validated and evaluated in the course of this dissertation considering many aspects of the modeling, simulation, design and verification of a low power embedded system implementing Adaptive Voltage and Frequency Scaling (AVFS) for energy saving.Item Open Access Ultra-high-speed digital-to-analog converter for optical communications(2019) Huang, Hao; Berroth, Manfred (Prof. Dr.-Ing.)In der vorliegenden Dissertation wird die Schaltungstechnik für schnelle DACs untersucht und ein DAC mit einer Umsetzungsrate bis zu 100 GS/s und 8 bit nomineller Auflösung in 28 nm CMOS Technologie entworfen. Um die Ausgangsbandbreite zu erhöhen, ist die Ausgangsstufe mit einer verteilten Struktur konstruiert. Dabei sind das Stromsummationsnetzwerk und die Taktverteilung an der DAC-Ausgangsstufe mittels künstlich konstruierten Leitungen realisiert, um die parasitären Kapazitäten auf die künstliche Leitung zu verteilen. Für die Charakterisierung des DACs ist ein 1 kByte Speicher integrierte, der zyklisch ausgelesen werden kann, um die Eingangsdatenströme für den DAC zu erzeugen. Die maximale Bandbreite beträgt 13 GHz bei einer Abtastrate von 100 GS/s. Die effektive Anzahl von Bits (engl. effective number of bits, ENOB) beträgt 5,3 bit bei niedrigen Ausgangsfrequenzen und reduziert sich auf 3,2 bit bei 24,9 GHz mit einer Abtastraten von 100 GS/s.Item Open Access Modeling the position and inflection of verbs in English to German machine translation(2018) Ramm, Anita; Fraser, Alexander (Prof. Dr.)Item Open Access Performance analysis of rate adaptive wireless communication system with regenerative relaying using low density parity check codes(2019) Chaoudhry, Bushra Bashir; Speidel, Joachim (Prof. Dr.-Ing.)Item Open Access A massively parallel combination technique for the solution of high-dimensional PDEs(2018) Heene, Mario; Pflüger, Dirk (Jun.-Prof. Dr.)The solution of high-dimensional problems, especially high-dimensional partial differential equations (PDEs) that require the joint discretization of more than the usual three spatial dimensions and time, is one of the grand challenges in high performance computing (HPC). Due to the exponential growth of the number of unknowns - the so-called curse of dimensionality, it is in many cases not feasible to resolve the simulation domain as fine as required by the physical problem. Although the upcoming generation of exascale HPC systems theoretically provides the computational power to handle simulations that are out of reach today, it is expected that this is only achievable with new numerical algorithms that are able to efficiently exploit the massive parallelism of these systems. The sparse grid combination technique is a numerical scheme where the problem (e.g., a high-dimensional PDE) is solved on different coarse and anisotropic computational grids (so-called component grids), which are then combined to approximate the solution with a much higher target resolution than any of the individual component grids. This way, the total number of unknowns being computed is drastically reduced compared to the case when the problem is directly solved on a regular grid with the target resolution. Thus, the curse of dimensionality is mitigated. The combination technique is a promising approach to solve high-dimensional problems on future exascale systems. It offers two levels of parallelism: the component grids can be computed in parallel, independently and asynchronously of each other; and the computation of each component grid can be parallelized as well. This reduces the demand for global communication and synchronization, which is expected to be one of the limiting factors for classical discretization techniques to achieve scalability on exascale systems. Furthermore, the combination technique enables novel approaches to deal with the increasing fault rates expected from these systems. With the fault-tolerant combination technique it is possible to recover from failures without time-consuming checkpoint-restart mechanisms. In this work, new algorithms and data structures are presented that enable a massively parallel and fault-tolerant combination technique for time-dependent PDEs on large-scale HPC systems. The scalability of these algorithms is demonstrated on up to 180225 processor cores on the supercomputer Hazel Hen. Furthermore, the parallel combination technique is applied to gyrokinetic simulations in GENE, a software for the simulation of plasma microturbulence in fusion devices.