05 Fakultät Informatik, Elektrotechnik und Informationstechnik

Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6

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Start date: 2020Institute: search.filters.UBSInstitut.Institut für Technische InformatikPublication Type: search.filters.UBSTyp.ZeitschriftenartikelSubject: search.filters.subject.004

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Now showing 1 - 10 of 25
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    Locking-enabled security analysis of cryptographic circuits
    (2024) Upadhyaya, Devanshi; Gay, Maël; Polian, Ilia
    Hardware implementations of cryptographic primitives require protection against physical attacks and supply chain threats. This raises the question of secure composability of different attack countermeasures, i.e., whether protecting a circuit against one threat can make it more vulnerable against a different threat. In this article, we study the consequences of applying logic locking, a popular design-for-trust solution against intellectual property piracy and overproduction, to cryptographic circuits. We show that the ability to unlock the circuit incorrectly gives the adversary new powerful attack options. We introduce LEDFA (locking-enabled differential fault analysis) and demonstrate for several ciphers and families of locking schemes that fault attacks become possible (or consistently easier) for incorrectly unlocked circuits. In several cases, logic locking has made circuit implementations prone to classical algebraic attacks with no fault injection needed altogether. We refer to this “zero-fault” version of LEDFA by the term LEDA, investigate its success factors in-depth and propose a countermeasure to protect the logic-locked implementations against LEDA. We also perform test vector leakage assessment (TVLA) of incorrectly unlocked AES implementations to show the effects of logic locking regarding side-channel leakage. Our results indicate that logic locking is not safe to use in cryptographic circuits, making them less rather than more secure.
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    A GPU-accelerated light-field super-resolution framework based on mixed noise model and weighted regularization
    (2022) Tran, Trung-Hieu; Sun, Kaicong; Simon, Sven
    Light-field (LF) super-resolution (SR) plays an essential role in alleviating the current technology challenge in the acquisition of a 4D LF, which assembles both high-density angular and spatial information. Due to the algorithm complexity and data-intensive property of LF images, LFSR demands a significant computational effort and results in a long CPU processing time. This paper presents a GPU-accelerated computational framework for reconstructing high-resolution (HR) LF images under a mixed Gaussian-Impulse noise condition. The main focus is on developing a high-performance approach considering processing speed and reconstruction quality. From a statistical perspective, we derive a joint ℓ1- ℓ2data fidelity term for penalizing the HR reconstruction error taking into account the mixed noise situation. For regularization, we employ the weighted non-local total variation approach, which allows us to effectively realize LF image prior through a proper weighting scheme. We show that the alternating direction method of the multipliers algorithm (ADMM) can be used to simplify the computation complexity and results in a high-performance parallel computation on the GPU Platform. An extensive experiment is conducted on both synthetic 4D LF dataset and natural image dataset to validate the proposed SR model’s robustness and evaluate the accelerated optimizer’s performance. The experimental results show that our approach achieves better reconstruction quality under severe mixed-noise conditions as compared to the state-of-the-art approaches. In addition, the proposed approach overcomes the limitation of the previous work in handling large-scale SR tasks. While fitting within a single off-the-shelf GPU, the proposed accelerator provides an average speedup of 2.46 ×and 1.57 ×for ×2and ×3SR tasks, respectively. In addition, a speedup of 77×is achieved as compared to CPU execution.
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    Thermal effects on monolithic 3D ferroelectric transistors for deep neural networks performance
    (2024) Kumar, Shubham; Chauhan, Yogesh Singh; Amrouch, Hussam
    Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.
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    Review on resistive switching devices based on multiferroic BiFeO3
    (2023) Zhao, Xianyue; Menzel, Stephan; Polian, Ilia; Schmidt, Heidemarie; Du, Nan
    This review provides a comprehensive examination of the state-of-the-art research on resistive switching (RS) in BiFeO3 (BFO)-based memristive devices. By exploring possible fabrication techniques for preparing the functional BFO layers in memristive devices, the constructed lattice systems and corresponding crystal types responsible for RS behaviors in BFO-based memristive devices are analyzed. The physical mechanisms underlying RS in BFO-based memristive devices, i.e., ferroelectricity and valence change memory, are thoroughly reviewed, and the impact of various effects such as the doping effect, especially in the BFO layer, is evaluated. Finally, this review provides the applications of BFO devices and discusses the valid criteria for evaluating the energy consumption in RS and potential optimization techniques for memristive devices.
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    Benchmarking the performance of portfolio optimization with QAOA
    (2022) Brandhofer, Sebastian; Braun, Daniel; Dehn, Vanessa; Hellstern, Gerhard; Hüls, Matthias; Ji, Yanjun; Polian, Ilia; Bhatia, Amandeep Singh; Wellens, Thomas
    We present a detailed study of portfolio optimization using different versions of the quantum approximate optimization algorithm (QAOA). For a given list of assets, the portfolio optimization problem is formulated as quadratic binary optimization constrained on the number of assets contained in the portfolio. QAOA has been suggested as a possible candidate for solving this problem (and similar combinatorial optimization problems) more efficiently than classical computers in the case of a sufficiently large number of assets. However, the practical implementation of this algorithm requires a careful consideration of several technical issues, not all of which are discussed in the present literature. The present article intends to fill this gap and thereby provides the reader with a useful guide for applying QAOA to the portfolio optimization problem (and similar problems). In particular, we will discuss several possible choices of the variational form and of different classical algorithms for finding the corresponding optimized parameters. Viewing at the application of QAOA on error-prone NISQ hardware, we also analyse the influence of statistical sampling errors (due to a finite number of shots) and gate and readout errors (due to imperfect quantum hardware). Finally, we define a criterion for distinguishing between ‘easy’ and ‘hard’ instances of the portfolio optimization problem.
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    Mixed-mode in-memory computing : towards high-performance logic processing in a memristive crossbar array
    (2025) Du, Nan; Polian, Ilia; Bengel, Christopher; Li, Kefeng; Chen, Ziang; Zhao, Xianyue; Hübner, Uwe; Chen, Li-Wei; Liu, Feng; Di Ventra, Massimiliano; Menzel, Stephan; Krüger, Heidemarie
    In-memory computing is a promising alternative to traditional computer designs, as it helps overcome performance limits caused by the separation of memory and processing units. However, many current approaches struggle with unreliable device behavior, which affects data accuracy and efficiency. In this work, the authors present a new computing method that combines two types of operations—those based on electrical resistance and those based on voltage-within each memory cell. This design improves reliability and avoids the need for expensive current measurements. A new software tool also helps automate the design process, supporting highly parallel operations in dense two-dimensional memory arrays. The approach balances speed and space, making it practical for advanced computing tasks. Demonstrations include a digital adder and a key part of encryption module, showing both strong performance and accuracy. This work offers a new direction for reliable and efficient in-memory computing systems with real-world applications.
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    Nontraditional design of dynamic logics using FDSOI for ultra-efficient computing
    (2023) Kumar, Shubham; Chatterjee, Swetaki; Dabhi, Chetan Kumar; Chauhan, Yogesh Singh; Amrouch, Hussam
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    Small delay fault testing with multiple voltages under variations : defect vs. fault coverage
    (2025) Jafarzadeh, Hanieh; Klemme, Florian; Amrouch, Hussam; Hellebrand, Sybille; Wunderlich, Hans-Joachim
    It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that Vmintesting poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under Vminis a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first algorithm for test pattern generation specifically tuned for Vmintesting which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. The patterns applicable to other voltage levels can be derived from the pattern set generated under extreme variations at low supply voltage. Experimental results demonstrate that the proposed method produces test patterns that outperform N-detection test sets in terms of test set volume and fault efficiency across different voltage levels.
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    Synergistic dynamical decoupling and circuit design for enhanced algorithm performance on near-term quantum devices
    (2024) Ji, Yanjun; Polian, Ilia
    Dynamical decoupling (DD) is a promising technique for mitigating errors in near-term quantum devices. However, its effectiveness depends on both hardware characteristics and algorithm implementation details. This paper explores the synergistic effects of dynamical decoupling and optimized circuit design in maximizing the performance and robustness of algorithms on near-term quantum devices. By utilizing eight IBM quantum devices, we analyze how hardware features and algorithm design impact the effectiveness of DD for error mitigation. Our analysis takes into account factors such as circuit fidelity, scheduling duration, and hardware-native gate set. We also examine the influence of algorithmic implementation details, including specific gate decompositions, DD sequences, and optimization levels. The results reveal an inverse relationship between the effectiveness of DD and the inherent performance of the algorithm. Furthermore, we emphasize the importance of gate directionality and circuit symmetry in improving performance. This study offers valuable insights for optimizing DD protocols and circuit designs, highlighting the significance of a holistic approach that leverages both hardware features and algorithm design for the high-quality and reliable execution of near-term quantum algorithms.
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    Stress-aware periodic test of interconnects
    (2022) Sadeghi-Kohan, Somayeh; Hellebrand, Sybille; Wunderlich, Hans-Joachim
    Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.