05 Fakultät Informatik, Elektrotechnik und Informationstechnik

Permanent URI for this collectionhttps://elib.uni-stuttgart.de/handle/11682/6

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Start date: 2020Subject: search.filters.subject.621.3Institute: search.filters.UBSInstitut.Institut für Technische Informatik

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Now showing 1 - 6 of 6
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    Nontraditional design of dynamic logics using FDSOI for ultra-efficient computing
    (2023) Kumar, Shubham; Chatterjee, Swetaki; Dabhi, Chetan Kumar; Chauhan, Yogesh Singh; Amrouch, Hussam
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    Modeling and investigating total ionizing dose impact on FeFET
    (2023) Sayed, Munazza; Ni, Kai; Amrouch, Hussam
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    Cryogenic embedded system to support quantum computing : from 5-nm FinFET to full processor
    (2023) Genssler, Paul R.; Klemme, Florian; Parihar, Shivendra Singh; Brandhofer, Sebastian; Pahwa, Girish; Polian, Ilia; Chauhan, Yogesh Singh; Amrouch, Hussam
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    Dependable reconfigurable scan networks
    (2022) Lylina, Natalia; Wunderlich, Hans-Joachim (Prof.)
    The dependability of modern devices is enhanced by integrating an extensive number of extra-functional instruments. These are needed to facilitate cost-efficient bring-up, debug, test, diagnosis, and adaptivity in the field and might include, e.g., sensors, aging monitors, Logic, and Memory Built-In Self-Test (BIST) registers. Reconfigurable Scan Networks (RSNs) provide a flexible way to access such instruments as well the device's registers throughout the lifetime, starting from post-silicon validation (PSV) through manufacturing test and finally during in-field operation. At the same time, the dependability properties of the system can be affected through an improper RSN integration. This doctoral project overcomes these problems and establishes a methodology to integrate dependable RSNs for a given system considering the most relevant dependability aspects, such as robustness, testability, and security compliance of RSNs.
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    Cryogenic in-memory computing for quantum processors using commercial 5-nm FinFETs
    (2023) Parihar, Shivendra Singh; Thomann, Simon; Pahwa, Girish; Chauhan, Yogesh Singh; Amrouch, Hussam
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    Systematic construction of deadlock-free routing for NoC using integer linear programming
    (2023) Liu, Shuang; Radetzki, Martin
    Network-on-Chip (NoC) presents a promising solution for on-chip communication in highly integrated System-on-Chips (SoCs). This work addresses critical challenges in NoC design, including routing construction, application mapping, and particularly the issue of deadlocks in the widely-used wormhole routing method. In this paper, an Integer Linear Programming (ILP) approach for deadlock-free routing is proposed, applicable to arbitrary network topologies. We systematically analyze deadlock-free routing construction for mesh and torus topologies under uniform random traffic and provide alternative solutions to turn models. In the context of application-specific NoCs, application mapping, and deadlock-free routing are integrated within a single ILP. Through evaluation with several benchmark applications, it is demonstrated that the ILP method consistently delivers optimal solutions and could obtain better results than various heuristic methods within an acceptable time. Fault tolerance is also explored and existing techniques are incorporated into the ILP approach. As an illustrative example, application mapping and a 1-link-fault-tolerant deadlock-free routing for the MP3 application on a mesh network is performed.