05 Fakultät Informatik, Elektrotechnik und Informationstechnik

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Start date: 2025End date: 2025Subject: search.filters.subject.530

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    Hardware-efficient preparation of architecture-specific graph states on near-term quantum computers
    (2025) Brandhofer, Sebastian; Polian, Ilia; Barz, Stefanie; Bhatti, Daniel
    Highly entangled quantum states are an ingredient in numerous applications in quantum computing. However, preparing these highly entangled quantum states on currently available quantum computers at high fidelity is limited by ubiquitous errors. Besides improving the underlying technology of a quantum computer, the scale and fidelity of these entangled states in near-term quantum computers can be improved by specialized compilation methods. In this work, the compilation of quantum circuits for the preparation of highly entangled architecture-specific graph states is addressed by defining and solving a formal model, i.e., a form of discrete constraint optimization. Our model incorporates information about gate cancellations, gate commutations, and accurate gate timing to determine an optimized graph state preparation circuit. Up to now, these aspects have only been considered independently of each other, typically applied to arbitrary quantum circuits. We quantify the quality of a generated state by performing stabilizer measurements and determining its fidelity. We show that our new method reduces the error when preparing a seven-qubit graph state by 3.5x on average compared to the state-of-the-art Qiskit solution. For a linear eight-qubit graph state, the error is reduced by 6.4x on average. The presented results highlight the ability of our approach to prepare higher fidelity or larger-scale graph states on gate-based quantum computing hardware.
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    Uncertainty quantification and propagation in surrogate-based Bayesian inference
    (2025) Reiser, Philipp; Aguilar, Javier Enrique; Guthke, Anneli; Bürkner, Paul-Christian
    Surrogate models are statistical or conceptual approximations for more complex simulation models. In this context, it is crucial to propagate the uncertainty induced by limited simulation budget and surrogate approximation error to predictions, inference, and subsequent decision-relevant quantities. However, quantifying and then propagating the uncertainty of surrogates is usually limited to special analytic cases or is otherwise computationally very expensive. In this paper, we propose a framework enabling a scalable, Bayesian approach to surrogate modeling with thorough uncertainty quantification, propagation, and validation. Specifically, we present three methods for Bayesian inference with surrogate models given measurement data. This is a task where the propagation of surrogate uncertainty is especially relevant, because failing to account for it may lead to biased and/or overconfident estimates of the parameters of interest. We showcase our approach in three detailed case studies for linear and nonlinear real-world modeling scenarios. Uncertainty propagation in surrogate models enables more reliable and safe approximation of expensive simulators and will therefore be useful in various fields of applications.
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    Fabrication and characterization of n-type Ge1-xSnx- and Si1-x-yGeySnx-on-SOI junctionless transistors
    (2025) Steuer, Oliver; Ghosh, Sayantan; Schwarz, Daniel; Oehme, Michael; Lehmann, Sebastian; Hübner, René; Fowley, Ciarán; Erbe, Artur; Zhou, Shengqiang; Helm, Manfred; Cuniberti, Gianaurelio; Prucnal, Slawomir; Georgiev, Yordan M.
    AbstractGe1-xSnx and Si1-x-yGeySnx alloys are promising materials for future nanoelectronic applications owing to their high carrier mobilities and CMOS compatibility. However, ternary Si1-x-yGeySnx transistors have only theoretically been discussed, and there are only a few reports on lateral n-type Ge1-xSnx transistors to benchmark their material performance. The low equilibrium solid solubility of Sn in Si1-xGex (less than 1 at%) requires device fabrication processes at temperatures below the growth temperature of Si1-x-yGeySnx (x > equilibrium solubility) or at non-equilibrium conditions. Therefore, Si-based processes need to be adjusted according to the materials requirements. A relatively easy-to-fabricate device concept are junctionless field effect transistors, which operate as a gated resistor. In this work, we use Ge0.94Sn0.06 and Si0.14Ge0.80Sn0.06 grown on silicon-on-insulator substrates to fabricate and characterize lateral n-type Ge1-xSnx and SiyGe1-x-ySnx junctionless field effect transistors. The transistors were structurally characterized by top-view scanning electron microscopy and cross-sectional transmission electron microscopy. Electrical characterizations by transfer characteristics show the first working n-type Ge1-xSnx and Si1-x-yGeySnx hetero-nanowire transistors, achieving on/off-current ratios of up to eight orders of magnitude.