Universität Stuttgart
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Item Open Access Scalable deterministic logic built-in self test(2006) Gherman, Valentin; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat.)The core-based design style of integrated circuits (ICs) helps to manage the development challenges brought by the ever increasing complexity of integrated systems and the ever tighter time-to-market. Nevertheless, test-related problems are still far away from having a unitary and satisfactory solution, especially in the system on a chip (SOC) context. For the test of ICs two reference approaches are available: external testing and built-in selftest (BIST), out of which a variety of hybrid test strategies are obtained by test resource partitioning (TRP). The final goal is to provide advantageous tradeoffs of the test evaluation indicators like: test development and application cost, hardware overhead, fault coverage, etc. BIST offers support for in-field, on-line, burn-in and at-speed test that is indispensable for delay fault testing. Moreover, tradeoffs between fault coverage, hardware overhead and test length are possible. External testing is characterized by flexibility, reduced hardware overhead and high fault coverage for a given test length. Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines the advantages of deterministic external testing and pseudo-random logic BIST (LBIST). Unfortunately, previously proposed DLBIST methods are unsuited for large ICs, since computation time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this work, a novel procedure for the development of the so-called bit-flipping DLBIST scheme is proposed, which has nearly linear complexity in terms of both computation time and memory consumption. This new method is based on the use of Binary Decision Diagrams (BDDs). The efficiency of the employed algorithms is demonstrated for industrial designs containing up to 2M gates. The embedded test sequences obtained by mapping deterministic cubes to pseudo-random sequences are also evaluated with respect to the coverage of non-target defects, which are modeled with the help of resistive bridging faults. The experimental results prove that both deterministic cubes and pseudo-random sequences are useful for detecting non-target defects. Moreover, possible tradeoffs between test length, hardware overhead, fault coverage and nontarget defect coverage are analyzed. This work additionally presents the results of extending the bit-flipping DLBIST scheme such that it also supports the transition fault testing besides the stuck-at fault testing. Transition faults model defects which are responsible for the incorrect operation of the core under test (CUT) at the desired speed. The importance of these defects is continuously enhanced by the ever increasing clock rates and integration density of today s circuits. Experimental results obtained for large industrial benchmark designs are reported. No pure DLBIST approach for the test of delay faults in circuits with standard scan design has been published so far. In order to decrease the logic overhead of DLBIST, an innovative way of constructing efficient implementations for the involved Boolean functions (e.g. bit-flipping functions) is presented. A key feature of these functions is their incomplete specification which is based on large don t care sets (sets of input assignments for which it does not matter whether they are mapped to 0 or 1 ). Reduced ordered Binary Decision Diagrams (ROBDD) are used for representing and manipulating the involved functions and multi-level implementations are obtained based on the use of free BDDs (FBDD). Experimental results show that for all the considered functions, implementations are found with a significant reduction of the gate count as compared to a state-of-the-art multi-level synthesys tool (SIS [Sen92]) or to methods offered by a state-of-the-art BDD package. This performance is due to a reduction of the node count in the corresponding FBDDs and a decrease in the average number of gates needed to implement the FBDD nodes. The experimental results obtained for large industrial benchmark designs show that DLBIST may be well suited for use in special segments of IC development, like the ones dealing with security chips or hard cores.Item Open Access Software based self test under memory, time and power constraints(2009) Zhou, Jun; Wunderlich, Hans-Joachim (Prof. Dr. habil.)The use of embedded system is ubiquitous in modern life, from automotive industry, robot techniques to the household appliances. As the core component of embedded systems, microprocessors play the central role in information processing, and fulfill several specialized tasks. The involvment in safty-critical applications requires high reliability of these systems. Test is known to be important for product quality and used to detect defects both during manufacturing or in-field scenario. In particular, the following aspects are crucial for microprocessor test. First, a low-cost test is preferrable in terms of hardware overhead, test time for example. To detect timing faults, testing at the system frequency, namely at-speed testing, is required. Design modification to incorporate hardware dedicated for test is not desirable due to potential performance degradation. Overtesting accounts for possible yield loss in that chips may fail the structural test, although those faults can never be sensitized in normal functional operations. The advent of software-based self-test solve these problems and therefore becomes the target of this work. However, constrained test generation is still of need. The dissertation looks into this aspect and proposes a novel SBST scheme, which optimizes memory, test application and power consumption at the same time without penalty of fault coverage. In addition, this work also presents a method to improve test quality of SBST through adding new instructions under the ASIP (application-specific instruction-set processor) framework.