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dc.contributor.authorEschermann, Bernhardde
dc.contributor.authorWunderlich, Hans-Joachimde
dc.description.abstractMost self-test techniques are implemented with so-called multifunctional test registers at any specific time either used for pattern generation or for response analysis. In a parallel self-test, however, test registers are used for pattern generation and response analysis simultaneously. In this paper a novel circuit structure for controllers with parallel self-test is presented, which does not result in a loss of fault coverage. By using a dedicated synthesis procedure, which considers the self-test hardware while generating the circuit structure instead of adding it after the design is completed ("synthesis for testability"), the self-test overhead can be kept low. The structure also facilitates realistic dynamic tests. As an example to illustrate the approach, the IEEE boundary scan controller is used.en
dc.subject.classificationSelbsttest , Prüfprogramm , Integrierte Schaltungde
dc.titleParallel self-test and the synthesis of control unitsen
ubs.fakultaetFakultätsübergreifend / Sonstige Einrichtungde
ubs.institutSonstige Einrichtungde
ubs.publikation.sourceProceedings / ETC 91. Berlin : VDE-Verl., 1991 - ISBN 3-8007-1778-6, S. 73-82de
Appears in Collections:15 Fakultätsübergreifend / Sonstige Einrichtung

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