Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-7920
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dc.contributor.authorEschermann, Bernhardde
dc.contributor.authorWunderlich, Hans-Joachimde
dc.date.accessioned2012-04-23de
dc.date.accessioned2016-03-31T11:44:38Z-
dc.date.available2012-04-23de
dc.date.available2016-03-31T11:44:38Z-
dc.date.issued1991de
dc.identifier.other369843738de
dc.identifier.urihttp://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73143de
dc.identifier.urihttp://elib.uni-stuttgart.de/handle/11682/7937-
dc.identifier.urihttp://dx.doi.org/10.18419/opus-7920-
dc.description.abstractMost self-test techniques are implemented with so-called multifunctional test registers at any specific time either used for pattern generation or for response analysis. In a parallel self-test, however, test registers are used for pattern generation and response analysis simultaneously. In this paper a novel circuit structure for controllers with parallel self-test is presented, which does not result in a loss of fault coverage. By using a dedicated synthesis procedure, which considers the self-test hardware while generating the circuit structure instead of adding it after the design is completed ("synthesis for testability"), the self-test overhead can be kept low. The structure also facilitates realistic dynamic tests. As an example to illustrate the approach, the IEEE boundary scan controller is used.en
dc.language.isoende
dc.rightsinfo:eu-repo/semantics/openAccessde
dc.subject.classificationSelbsttest , Prüfprogramm , Integrierte Schaltungde
dc.subject.ddc621.3de
dc.titleParallel self-test and the synthesis of control unitsen
dc.typeconferenceObjectde
dc.date.updated2012-08-10de
ubs.fakultaetFakultätsübergreifend / Sonstige Einrichtungde
ubs.institutSonstige Einrichtungde
ubs.opusid7314de
ubs.publikation.sourceProceedings / ETC 91. Berlin : VDE-Verl., 1991 - ISBN 3-8007-1778-6, S. 73-82de
ubs.publikation.typKonferenzbeitragde
Appears in Collections:15 Fakultätsübergreifend / Sonstige Einrichtung

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