The integration of test and high level synthesis in a general design environment

Abstract

This paper describes the integration of new tools for both test and synthesis of integrated circuits. The presented design system CADDY (Carlsruhe Digital Design System) automatically transforms a functional description into a circuit structure. Besides this logic synthesis the system also automatically integrates a complete or incomplete scan path. The software tool PROTEST (PRObabilistic TESTability analysis tool) determines the random testability of the combinational parts of synthesized circuits and suggests optimized input signal probabilities to minimize the necessary test length. To generate these test patterns on chip a specific test hardware is proposed.