Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-7952
Authors: Hellebrand, Sybille
Wunderlich, Hans-Joachim
Title: Synthesis of self-testable controllers
Issue Date: 1994
metadata.ubs.publikation.typ: Konferenzbeitrag
metadata.ubs.publikation.source: Tual, Jean-Pierre (Hrsg.): Proceedings / The European Design and Test Conference. Los Alamitos, Calif. : IEEE Computer Soc. Pr., 1994. - ISBN 0-8186-5410-4, S. 580-585. URL http://dx.doi.org./10.1109/EDTC.1994.326815
URI: http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73588
http://elib.uni-stuttgart.de/handle/11682/7969
http://dx.doi.org/10.18419/opus-7952
Abstract: The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal too. The self-testable structure for a given finite state machine specification is derived from all appropriate reaiization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm to determine realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach.
Appears in Collections:15 Fakultätsübergreifend / Sonstige Einrichtung

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