20 Gbit/s 2:1 multiplexer using 0.3 μm gate length double pulse doped quantum well GaAs/AlGaAs transistors

Abstract

A high speed 2:1 multiplexer circuit in source coupled FET logic has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3μm gate length. First results show a data rate of over 20 Gbit/s at 5 V supply voltage and 250 mW power consumption. The output voltage swing is adjustable between 0.3 V and 0.8 V for a 50 Ohm load. The out-put level can be varied between +1 V an -1 V. Comparison between simulation and measurement shows very good agreement.