Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-8197
Authors: Wang, Zhigong
Berroth, Manfred
Seibel, Jörg
Hofmann, Peter
Hülsmann, Axel
Köhler, Klaus
Raynor, Brian
Schneider, Joachim
Title: 19 GHz monolithic integrated clock recovery using PLL and 0.3 μm gate-length quantum-well HEMTs
Issue Date: 1994
metadata.ubs.publikation.typ: Konferenzbeitrag
metadata.ubs.publikation.source: Wuorinen, John H. (Hrsg.): Digest of technical papers / 1994 IEEE International Solid-State Circuits Conference. Piscataway, NJ : IEEE Service Center, 1994 (Digest of technical papers / IEEE International Solid State Circuits Conference 37). - ISBN 0-7803-1844-7, S. 118-119
URI: http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-92515
http://elib.uni-stuttgart.de/handle/11682/8214
http://dx.doi.org/10.18419/opus-8197
Abstract: ICs for optical data links have been developed for bit rates between 10 and 200 Gb/s. The only exception was the clock recovery (CR) IC at these high bit rates. In fact, the IC realization of CR is generally accepted as the weak point of high-speed system integration. While the bit rates of some ICs reach up to 40 Gb/s, monolithic ICs for a full CR function are limited to 2.5 Gb/s. The monolithic IC described here, for CR with a PLL including a full-balanced VCO, is based on the IC reported by Wang et. al. (1993). Clock frequencies up to 19 GHz are recovered with the IC reported here.
Appears in Collections:15 Fakultätsübergreifend / Sonstige Einrichtung

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