The random pattern testability of programmable logic arrays
| dc.contributor.author | Wunderlich, Hans-Joachim | de |
| dc.date.accessioned | 2012-05-04 | de |
| dc.date.accessioned | 2016-03-31T11:44:42Z | |
| dc.date.available | 2012-05-04 | de |
| dc.date.available | 2016-03-31T11:44:42Z | |
| dc.date.issued | 1987 | de |
| dc.description.abstract | An efficient Monte Carlo Algorithm is presented estimating the detection probability of each stuck at fault of a PLA. Furthermore for each primary input of the PLA the optimal probability is computed to set this input to logical "1". Using those unequiprobable input probabilities the necessary test set can be reduced by orders of magnitude. Thus a seIftest by optimized random patterns is possible even if the circuit contains large PLAs preventing a conventional random test. | en |
| dc.identifier.other | 37015505X | de |
| dc.identifier.uri | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73504 | de |
| dc.identifier.uri | http://elib.uni-stuttgart.de/handle/11682/7961 | |
| dc.identifier.uri | http://dx.doi.org/10.18419/opus-7944 | |
| dc.language.iso | en | de |
| dc.rights | info:eu-repo/semantics/openAccess | de |
| dc.subject.classification | Selbsttest , Integrierte Schaltung , Fehlererkennung | de |
| dc.subject.ddc | 621.3 | de |
| dc.title | The random pattern testability of programmable logic arrays | en |
| dc.type | conferenceObject | de |
| ubs.fakultaet | Fakultätsübergreifend / Sonstige Einrichtung | de |
| ubs.institut | Sonstige Einrichtung | de |
| ubs.opusid | 7350 | de |
| ubs.publikation.source | Proceedings / 1987 IEEE International Conference on Computer Design. Washington, DC : Computer Soc. of the IEEE, 1987. - ISBN 0-8186-0802-1, S. 682-685 | de |
| ubs.publikation.typ | Konferenzbeitrag | de |