Hardware-efficient preparation of architecture-specific graph states on near-term quantum computers

Abstract

Highly entangled quantum states are an ingredient in numerous applications in quantum computing. However, preparing these highly entangled quantum states on currently available quantum computers at high fidelity is limited by ubiquitous errors. Besides improving the underlying technology of a quantum computer, the scale and fidelity of these entangled states in near-term quantum computers can be improved by specialized compilation methods. In this work, the compilation of quantum circuits for the preparation of highly entangled architecture-specific graph states is addressed by defining and solving a formal model, i.e., a form of discrete constraint optimization. Our model incorporates information about gate cancellations, gate commutations, and accurate gate timing to determine an optimized graph state preparation circuit. Up to now, these aspects have only been considered independently of each other, typically applied to arbitrary quantum circuits. We quantify the quality of a generated state by performing stabilizer measurements and determining its fidelity. We show that our new method reduces the error when preparing a seven-qubit graph state by 3.5x on average compared to the state-of-the-art Qiskit solution. For a linear eight-qubit graph state, the error is reduced by 6.4x on average. The presented results highlight the ability of our approach to prepare higher fidelity or larger-scale graph states on gate-based quantum computing hardware.