Haberl, Oliver F.Wunderlich, Hans-Joachim2012-04-272016-03-312012-04-272016-03-311989370124480http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73395http://elib.uni-stuttgart.de/handle/11682/7954http://dx.doi.org/10.18419/opus-7937In recent years, many built-in self-test techniques have been proposed based on feedback shift-registers for pattern generation and signature analysis. But in general, these test-registers cannot test several modules of the chip concurrently, and they have to be controlled by external automatic test equipment. The authors propose a method to integrate additional test-control logic into the chip. On the basis of a register-transfer description of the circuit, the test control is derived, and a corresponding finite automation is synthesized. A hardware implementation is proposed, resulting in circuits where the entire self-test only consists in activating the test mode and clocking and evaluating the overall signature.eninfo:eu-repo/semantics/openAccessFehlererkennung , Selbsttest , VLSI621.3conferenceObject