7.5 Gb/s monolithically integrated clock recovery using PLL and 0.3 μM gate length quantum well HEMTs

Wang, ZhigongBerroth, ManfredNowotny, UlrichHofmann, PeterHülsmann, AxelKöhler, KlausRaynor, BrianSchneider, Joachim2014-05-122016-03-312014-05-122016-03-311993414109619http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-92580http://elib.uni-stuttgart.de/handle/11682/8221http://dx.doi.org/10.18419/opus-8204A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO has been introduced. The VCO has a centre oscillating frequency of about 7.5 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at the bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at the supply voltage of -5 V.eninfo:eu-repo/semantics/openAccessTaktrückgewinnung , HEMT , Galliumarsenid , Aluminiumarsenid , Mischkristall , Phasenregelkreis621.37.5 Gb/s monolithically integrated clock recovery using PLL and 0.3 μM gate length quantum well HEMTsconferenceObject2014-09-02