Eschermann, BernhardWunderlich, Hans-Joachim2012-04-232016-03-312012-04-232016-03-311990369848993http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73199http://elib.uni-stuttgart.de/handle/11682/7941http://dx.doi.org/10.18419/opus-7924A synthesis procedure for self-testable finite state machines is presented. Testability comes under consideration when the behavioral description of the circuit is being transformed into a structural description. To this end, a novel state encoding algorithm, as well as a modified self-test architecture, is developed. Experimental results show that this approach leads to a significant reduction of hardware overhead. Self-testing circuits generally employ linear feedback shift registers for pattern generation. The impact of choosing a particular feedback polynomial on the state encoding is discussed.eninfo:eu-repo/semantics/openAccessSelbsttest , VLSI , Integrierte Schaltung621.3conferenceObject2012-08-10