Brain-inspired hyperdimensional computing for robust and lightweight machine learning

Abstract

This thesis investigates hyperdimensional computing (HDC) as an emerging machine learning method. HDC’s integration with in-memory computing architectures is explored to address challenges at both application and technology levels, particularly in the domain of semiconductor test and reliability. HDC’s inherent redundancy offers robustness to errors, making it suitable for applications like transistor aging modeling, circuit recognition, and wafer map defect pattern classification. However, it is computationally demanding for off-the-shelf systems, motivating the development of efficient architectures using FPGA, custom chips, and FeFET-based in-memory computing. This integration bridges the gap between technology and application levels, enhancing efficiency while addressing reliability trade-offs. The work also adapts HDC training to mitigate errors from non-volatile memories, ensuring robust performance. Overall, the thesis demonstrates HDC’s potential for lightweight, efficient ML systems and novel applications, overcoming limitations of traditional approaches.