Browsing by Author "Eschermann, Bernhard"

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Open Access
Emulation of scan paths in sequential circuit synthesis
(1991) Eschermann, Bernhard; Wunderlich, Hans-Joachim
Scan paths are generally added to a sequential circuit in a final design for testability step. We present an approach to incorporate the behavior of a scan path during circuit synthesis, thus avoiding to implement the scan path shift register as a separate structural entity. The shift transitions of the scan path are treated as a part of the system functionality. Depending on the minimization strategy for the system logic, either the delay or the area of the circuit can be reduced compared to a conventional scan path. which may be interpreted as a special case of realizing the combinational logic. The approach is also extended to partial scan paths. It is shown that the resulting structure is fully testable and test patterns can be efficiently produced by a combinational test generator. The advantages of the approach are illustrated with a collection of finite state machine examples.
Open Access
Optimized synthesis of self-testable finite state machines
(1990) Eschermann, Bernhard; Wunderlich, Hans-Joachim
A synthesis procedure for self-testable finite state machines is presented. Testability comes under consideration when the behavioral description of the circuit is being transformed into a structural description. To this end, a novel state encoding algorithm, as well as a modified self-test architecture, is developed. Experimental results show that this approach leads to a significant reduction of hardware overhead. Self-testing circuits generally employ linear feedback shift registers for pattern generation. The impact of choosing a particular feedback polynomial on the state encoding is discussed.
Open Access
Optimized synthesis techniques for testable sequential circuits
(1992) Eschermann, Bernhard; Wunderlich, Hans-Joachim
The authors describe a synthesis approach that maps a behavioral finite state machine (FSM) description into a testable gate-level structure. The term testable, besides implying the existence of tests, also means that the application of test patterns is facilitated. Depending on the test strategy, the state registers of the FSM are modified, e.g. as scan path or self-test registers. The additional functionality of these state registers is utilized in system mode by interpreting them as smart state registers, capable of producing certain state transitions on their own. To make the best use of such registers, the authors propose a novel state encoding strategy based on an analytic formulation of the coding constraint satisfaction problem as a quadratic assignment problem. An additional minimization potential can be exploited by appropriately choosing the pattern generator for self-testable designs. Experimental results indicate that, compared with conventional design for testability approaches, significant savings are possible this way.
Open Access
Parallel self-test and the synthesis of control units
(1991) Eschermann, Bernhard; Wunderlich, Hans-Joachim
Most self-test techniques are implemented with so-called multifunctional test registers at any specific time either used for pattern generation or for response analysis. In a parallel self-test, however, test registers are used for pattern generation and response analysis simultaneously. In this paper a novel circuit structure for controllers with parallel self-test is presented, which does not result in a loss of fault coverage. By using a dedicated synthesis procedure, which considers the self-test hardware while generating the circuit structure instead of adding it after the design is completed ("synthesis for testability"), the self-test overhead can be kept low. The structure also facilitates realistic dynamic tests. As an example to illustrate the approach, the IEEE boundary scan controller is used.
Open Access
A synthesis approach to reduce scan design overhead
(1990) Eschermann, Bernhard; Wunderlich, Hans-Joachim
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Open Access
A unified approach for the synthesis of self-testable finite state machines
(1991) Eschermann, Bernhard; Wunderlich, Hans-Joachim
Conventionally self-test hardware is added after synthesis is completed. For highly sequential circuits like controllers this design method either leads to high hardware overheads or compromises fault coverage. In this paper we outline a unified approach for considering self-test hardware like pattern generators and signature registers during synthesis. Three novel target structures are presented, and a method for designing parallel self-testable circuits is discussed in more detail. For a collection of benchmark circuits we show that hardware overheads for self-testable circuits can be significantly reduced this way without sacrificing testability.