Browsing by Author "Haberl, Oliver F."

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Open Access
Generating pseudo-exhaustive vectors for external testing
(1990) Hellebrand, Sybille; Wunderlich, Hans-Joachim; Haberl, Oliver F.
Over the past years special chips for external tests have been successfully used for random pattern testing. The authors present a technique for combining the advantages of such a low-cost test with the advantages of pseudoexhaustive testing, which are enhanced fault coverage and simplified test pattern generation. To achieve this goal, two tasks are accomplished. First, an algorithm is developed for pseudoexhaustive test pattern generation, which ensures a feasible test length. Second, a chip design for applying these test patterns to a device under test is presented. The chip is programmed by the output of the proposed algorithm and controls the entire test. The technique is first applied to devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.
Open Access
The synthesis of self-test control logic
(1989) Haberl, Oliver F.; Wunderlich, Hans-Joachim
In recent years, many built-in self-test techniques have been proposed based on feedback shift-registers for pattern generation and signature analysis. But in general, these test-registers cannot test several modules of the chip concurrently, and they have to be controlled by external automatic test equipment. The authors propose a method to integrate additional test-control logic into the chip. On the basis of a register-transfer description of the circuit, the test control is derived, and a corresponding finite automation is synthesized. A hardware implementation is proposed, resulting in circuits where the entire self-test only consists in activating the test mode and clocking and evaluating the overall signature.
Open Access
TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control
(1990) Ströle, Albrecht P.; Wunderlich, Hans-Joachim; Haberl, Oliver F.
A chip is presented that generates weighted random patterns, applies them to a circuit under test and evaluates the test responses. The generated test patterns correspond to multiple sets of weights. Test response evaluation is done by signature analysis. The chip can easily be connected to a micro computer and thus constitutes the key element of a low-cost test equipment.