Browsing by Author "Lang, Manfred"

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    10-20 Gbit/s GaAs/AlGaAs HEMT ICs for high speed data links
    (1992) Berroth, Manfred; Hurm, Volker; Lang, Manfred; Ludwig, Manfred; Nowotny, Ulrich; Wang, Zhigong; Wennekers, Peter; Hülsmann, Axel; Kaufel, Gudrun; Köhler, Klaus; Raynor, Brian; Schneider, Joachim
    A set of ICs has been developed for high-speed data links at data rates above 10 Gbit/s. A recessed gate process for double pulse doped quantum well transistors has been used with e-beam written 0.3- μm gates. A 4 bit multiplexer and a laser diode driver for the transmitter as well as a transimpedance amplifier, bit synchronizer, and 4 bit demultiplexer for the receiver have been successfully operated with data rates up to 20 Gbit/s.
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    11.6 Gbps 1:4 demultiplexer using double pulse doped quantum well GaAs/AlGaAs transistors
    (1991) Lang, Manfred; Nowotny, Ulrich; Berroth, Manfred
    An ultrahigh speed 4 bit demultiplexer circuit has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3 mu m gate length. First results show a data rate of 11.6 Gbit/s and a power consumption of 165 mW at 0.85 V supply voltage, including four 50 Omega buffers.
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    20 Gb/s monolithic integrated clock recovery and data decision
    (1994) Wang, Zhigong; Berroth, Manfred; Hurm, Volker; Lang, Manfred; Hofmann, Peter; Hülsmann, Axel; Köhler, Klaus; Raynor, Brian; Schneider, Joachim
    An IC for 20 Gb/s clock recovery and data decision was realised using 0.3 m gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals have been obtained. The 2x2 mm 2 IC has a power consumption of about 0.5 W at -3 volt supply voltage.
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    20 Gbit/s 2:1 multiplexer using 0.3 μm gate length double pulse doped quantum well GaAs/AlGaAs transistors
    (1991) Nowotny, Ulrich; Lang, Manfred; Berroth, Manfred; Hurm, Volker; Hülsmann, Axel; Kaufel, Gudrun; Köhler, Klaus; Raynor, Brian; Schneider, Joachim
    A high speed 2:1 multiplexer circuit in source coupled FET logic has been developed and fabricated using a recessed gate process for enhancement and depletion transistors with 0.3μm gate length. First results show a data rate of over 20 Gbit/s at 5 V supply voltage and 250 mW power consumption. The output voltage swing is adjustable between 0.3 V and 0.8 V for a 50 Ohm load. The out-put level can be varied between +1 V an -1 V. Comparison between simulation and measurement shows very good agreement.