Browsing by Author "Schneider, Eric"

Now showing 1 - 4 of 4

Open Access
Adaptive simulationsbasierte Diagnose von Verzögerungsfehlern in kombinatorischen Schaltungen
(2012) Schneider, Eric
Bei der Chipproduktion können systematische Defekte auftreten, die das Zeitverhalten der Schaltung beeinflussen, sodass die Chips bei Echtzeitbedingungen kleinste Verzögerungsfehler (sog. Small Delays) verursachen. Um fehleranfällige Stellen innerhalb eines Chips ausfindig zu machen und das Layout und die Prozessparameter bei der Herstellung entsprechend anpassen zu können, müssen fehlerhafte Chips diagnostiziert werden. Die genaue logische Diagnose von kleinsten Verzögerungsfehlern ist aufgrund der hohen Komplexität sehr aufwändig, weshalb hierbei typischerweise auf einfache Fehlermodelle, wie z.B. dem Transitionsfehlermodell, zurückgegriffen wird, welche Small Delay Fehler jedoch nur unzureichend abdecken und bei Variationen im Chip irreführend sein können. In dieser Arbeit wird ein neuartiges logisches Diagnoseverfahren vorgestellt, welches mit Hilfe von präziser Zeitsimulation kleinste Verzögerungsfehler in kombinatorischen Schaltkreisen auch unter Variationen effizient und stabil diagnostizieren kann. Hierbei werden die initialen Fehlerkandidaten zunächst mit Hilfe von Effect-Cause Methoden reduziert und anschließend die Defektstelle, sowie die Defektgröße, durch eine selektive Simulation der verbleibenden Kandidaten mit wenigen Simulationsschritten bestimmt. Die Diagnostizierfähigkeit der Methode wird anhand von Experimenten mit gängigen Benchmark Schaltkreisen, sowie industriellen Schaltkreisen gezeigt.
Open Access
CUDA-accelerated delay fault simulation
(2011) Schneider, Eric
In todays VLSI chip manufacturing processes variations occur, that may manifest as delay defects and affect the timing behaviour of the circuit. In general, these delay faults only occur under at-speed test conditions and it requires special effort to simulate them. Since fault simulation is inherently parallelizable, NVIDIAs Compute Unified Device Architecture (CUDA) is used for utilizing general purpose graphics processing units (GPGPUs) in order to exploit available parallelism. The goal of this study thesis was the implementation of a delay fault simulator to simulate the behaviour of small delay faults on CUDA devices and its integration into a diagnosis framework for application of the Partially Overlapping Impact couNTER (POINTER) algorithm. A series of experiments was performed to observe the diagnosability of the delay faults.
Open Access
Host firewall on AUTOSAR Adaptive based vehicle computers & domain ECUs
(2022) Schneider, Eric
Setting up firewalls without additional tooling can be inefficient and complicated. In this paper a prototype will be presented that allows the configuration of an ECU host firewall based on a well defined configuration file. This firewall is designed to run on vehicle computers and smart components inside cars that run the AUTOSAR Adaptive platform. The goal is to simplify firewall setup to secure these components against malicious traffic in the network and to prevent attack vectors that try to exploit physical access to the system. The presented prototype will be using nftables and the netfilter subsystem to set up both stateless and stateful filtering rules for both incoming and forwarded traffic. Packet inspection will also be evaluated in this context and approaches to filtering of the high level SOME/IP protocol will be presented. Example rulesets for both regular ECUs that are running the AUTOSAR Adaptive platform as well as an example for network separation will be provided. A short introduction to the AUTOSAR IAM concept will be given along with a comparison between it and the presented Firewall concept will be drawn. Keywords: AUTOSAR Adaptive Platform, Firewall, IAM, WSL2
Open Access
Multi-level simulation of nano-electronic digital circuits on GPUs
(2019) Schneider, Eric; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat. habil.)
Simulation of circuits and faults is an essential part in design and test validation tasks of contemporary nano-electronic digital integrated CMOS circuits. Shrinking technology processes with smaller feature sizes and strict performance and reliability requirements demand not only detailed validation of the functional properties of a design, but also accurate validation of non-functional aspects including the timing behavior. However, due to the rising complexity of the circuit behavior and the steady growth of the designs with respect to the transistor count, timing-accurate simulation of current designs requires a lot of computational effort which can only be handled by proper abstraction and a high degree of parallelization. This work presents a simulation model for scalable and accurate timing simulation of digital circuits on data-parallel graphics processing unit (GPU) accelerators. By providing compact modeling and data-structures as well as through exploiting multiple dimensions of parallelism, the simulation model enables not only fast and timing-accurate simulation at logic level, but also massively-parallel simulation with switch level accuracy. The model facilitates extensions for fast and efficient fault simulation of small delay faults at logic level, as well as first-order parametric and parasitic faults at switch level. With the parallelization on GPUs, detailed and scalable simulation is enabled that is applicable even to multi-million gate designs. This way, comprehensive analyses of realistic timing-related faults in presence of process- and parameter variations are enabled for the first time. Additional simulation efficiency is achieved by merging the presented methods in a unified simulation model, that allows to combine the unique advantages of the different levels of abstraction in a mixed-abstraction multi-level simulation flow to reach even higher speedups. Experimental results show that the implemented parallel approach achieves unprecedented simulation throughput as well as high speedup compared to conventional timing simulators. The underlying model scales for multi-million gate designs and gives detailed insights into the timing behavior of digital CMOS circuits, thereby enabling large-scale applications to aid even highly complex design and test validation tasks.