Browsing by Author "Wunderlich, Hans-Joachim"

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Open Access
An analytical approach to the partial scan problem
(1990) Kunzmann, Arno; Wunderlich, Hans-Joachim
The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.
Open Access
Automatische Synthese selbsttestbarer Moduln für hochkomplexe Schaltungen
(1989) Kesel, Frank; Wunderlich, Hans-Joachim
Für den Test hochkomplexer digitaler Schaltungen bieten sich Selbsttestverfahren an, die auf multifunktionalen linear rückgekoppelten Schieberegistern beruhen. Diese erzeugen Pseudozufallsmuster und komprimieren die Testantworten zu einer Signatur. Durch einen automatischen Einbau der Selbsttestausstattung kann die Korrektheit des Entwurfs gewährleistet werden. Im vorliegenden Beitrag wird ein Verfahren vorgestellt, mit welchem sich multifunktionale Registerschaltungen automatisch synthetisieren lassen, welche gleich- und ungleichverteilte Pseudozufallsmuster erzeugen und die Testantworten durch Signaturanalyse komprimieren. Sie werden als Standardzellen erzeugt und können automatisch plaziert und verdrahtet werden.
Open Access
Automatisierung des Entwurfs vollständig testbarer Schaltungen
(1988) Hellebrand, Sybille; Wunderlich, Hans-Joachim
Die Kosten für die Testvorbereitung, Testerzeugung und Testdurchführung wachsen überproportional mit der Komplexität anwendungsspezifischer Schaltungen, und die Teststrategie sollte daher bereits in einer sehr frühen Phase des Schaltungsentwurfs festgelegt und berücksichtigt werden. In diesem Artikel werden logische Grundzellen und Algorithmen zur Unterstützung des pseudo-erschöpfenden Tests vorgestellt. Diese Teststrategie hat den Vorteil, daß die äußerst rechenzeitaufwendige Testmustererzeugung entfällt und zugleich eine vollständige Fehlererfassung auf Gatterebene garantiert ist. Die vorgestellten Grundzellen dienen der Zerlegung der Gesamtschaltung in erschöpfend testbare Teile, die präsentierten Algorithmen sollen diese Segmentierungszellen so plazieren, daß der Mehraufwand an Silizium gering bleibt. Hierzu wurden Varianten sogenannter "Hill-Climbing" und "Simulated-Annealing"-Verfahren entwickelt.
Open Access
A common approach to test generation and hardware verification based on temporal logic
(1991) Kropf, Thomas; Wunderlich, Hans-Joachim
Hardware verification and sequential test generation are aspects of the same problem, namely to prove the equal behavior determined by two circuit descriptions. During test generation, this attempt succeeds for the faulty and fault free circuit if redundancy exists, and during verification it succeeds, if the implementation is correct with regard to its specification. This observation can be used to cross-fertilize both areas, which been treated separately up to now. In this paper, a common formal framework for hardware verification and sequential test pattern generation is presented, which is based on modeling the circuit behavior with temporal logic. In addition, a new approach to cope with non resetable flipflops in sequential test generation is proposed, which is not restricted to stuck-at faults. Based on this verification view, it is possible to provide the designer with one tool for checking circuit correctness and generating test patterns. Its first implementation and application is also described.
Open Access
A complete design-for-test scheme for reconfigurable scan networks
(2023) Lylina, Natalia; Wang, Chih-Hao; Wunderlich, Hans-Joachim
Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing system-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme . It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.
Open Access
Configuring flip-flops to BIST registers
(1994) Ströle, Albrecht P.; Wunderlich, Hans-Joachim
Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimizations is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that can be controlled in the same way are assembled to test registers. Finally, a test schedule at RT level is constructed and a minimal set of test control signals is determined. The presented approach can reduce both BIST hardware overhead and test application time. It is applicable to control units and circuits produced by control oriented synthesis where an RT description is not available. Considerable gains can also be obtained if existing RT structures are reconfigured for self-testing in the described way.
Open Access
Design automation of random testable circuits
(1985) Kunzmann, Arno; Wunderlich, Hans-Joachim
This paper describes the integration of a new tool for testability measurement and improvement into a design system for integrated circuits. The involved design system, CADDY (Carlsruhe Digital Design System), uses a functional description of a circuit written in a PASCAL like language and synthesizes a list of nets and real logical components. In this resulting structure all storing elements are configured as a scan path automatically. Therefore testability analysis and test generation may be restricted to pure combinational networks. This is done by the software tool PROTEST (Probabilistic Testability Analysis). PROTEST determines the testability of a combinational circuit by random patterns, it computes the test length necessary to reach a given fault coverage with an also given confidence, and it proposes modifications of the random pattern sets, which leads to decreasing test lengths.
Open Access
The design of random-testable sequential circuits
(1989) Wunderlich, Hans-Joachim
A method is described for selecting a minimal set of directly accessible flip-flops. Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. An algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. The entire approach is validated with the help of examples. Only 10-40% of the flip-flops have to be integrated into a partial scan path or into a built-in self-test register to obtain nearly complete fault coverage by weighted random patterns.
Open Access
The effectiveness of different test sets for PLAs
(1990) Maxwell, Peter C.; Wunderlich, Hans-Joachim
It has been theoretically demonstrated that the single stuck-at fault model for a PLA does not cover as many faults as the single crosspoint model. What has not been demonstrated is the real relative effectiveness of test sets generated using these models. This paper presents the results of a study involving presenting a number of test sets to fabricated PLAs to determine their effectiveness. The test sets included weighted random patterns, of particular interest owing to PLAs being random resistant. Details are given of a method to generate weights, taking into account a PLA's structure.
Open Access
An efficient procedure for the synthesis of fast self-testable controller structures
(1994) Hellebrand, Sybille; Wunderlich, Hans-Joachim
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for rest purposes. This leads to some serious drawbacks concerning the fault coverage, the system speed and the area overhead. A synthesis technique is presented which uses the additional test register also to implement the system function by supporting self-testable pipeline-like controller structures. It will be shown, that if the need of two different registers in the final structure is already taken into account during synthesis, then the overall number of flipflops can be reduced, and the fault coverage and system speed call be enhanced. The presented algorithm constructs realizations of a given finite state machine a self-testable structure. The efficiency of the procedure is ensured by a very precise characterization of the space of suitable realizations, which avoids the computational overhead of previously published algorithms.
Open Access
Efficient test set evaluation
(1992) Wunderlich, Hans-Joachim; Warnecke, Maren
The fault coverage obtained by a set of test patterns is usually determined by expensive fault simulation. Even when using fault dropping techniques, fault simulation provides more information than actually needed. For each fault, the pattern is determined which detects this fault first. This is mainly redundant information if diagnosis is not required. One can dispense with this high resolution and restrict interest to the set of faults which is detected by a set of patterns. It is shown theoretically and practically that this information is obtainable in an highly efficient way.
Open Access
Emulation of scan paths in sequential circuit synthesis
(1991) Eschermann, Bernhard; Wunderlich, Hans-Joachim
Scan paths are generally added to a sequential circuit in a final design for testability step. We present an approach to incorporate the behavior of a scan path during circuit synthesis, thus avoiding to implement the scan path shift register as a separate structural entity. The shift transitions of the scan path are treated as a part of the system functionality. Depending on the minimization strategy for the system logic, either the delay or the area of the circuit can be reduced compared to a conventional scan path. which may be interpreted as a special case of realizing the combinational logic. The approach is also extended to partial scan paths. It is shown that the resulting structure is fully testable and test patterns can be efficiently produced by a combinational test generator. The advantages of the approach are illustrated with a collection of finite state machine examples.
Open Access
Erfassung und Modellierung komplexer Funktionsfehler in Mikroelektronik-Bauelementen
(1992) Stern, Olaf; Wunderlich, Hans-Joachim
Es wird ein Verfahren vorgestellt, das für die Grundzellen einer Zellbibliothek layoutabhängig die möglichen Fehlfunktionen bestimmt, die durch Fertigungsfehler verursacht werden können. Eingabe für das Verfahren sind neben dem Layout einer Zelle die Prozeßparameter und die Defektverteilungen, Ausgabe sind die realistischen Fehlfunktionen mit ihren Auftrittswahrscheinlichkeiten. Damit können Testerzeugung und Testablauf beschleunigt, schwer testbare Fehler bestimmt und ihre Ursachen lokalisiert und beseitigt werden.
Open Access
Error masking in self-testable circuits
(1990) Ströle, Albrecht P.; Wunderlich, Hans-Joachim
The effects of error masking in a number of signature registers are analyzed. It is shown that a self-test can always be scheduled such that evaluating signatures only at the end of the complete test execution is sufficient. A method for computing the probability of a fault leading to at least one faulty signature in a set of self-test registers is presented. This method allows the computation of the fault coverage with respect to the complete test execution. A minimal subset of all self-test registers can be selected so that only the signatures of these self-test registers have to be evaluated and the fault coverage is almost not affected. The benefits of this approach are a smaller number of self-test registers in the scan path, a smaller number of signatures to be evaluated, a simplified test control unit, and hence a significant reduction in tie hardware required for built-in self-test structures. The proposed method is illustrated by an example and validated by simulation.
Open Access
Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits
(1988) Wunderlich, Hans-Joachim; Hellebrand, Sybille
A method based on linear feedback shift registers over finite fields is presented to generate for a natural number n a pattern sequence with minimal length detecting each m-multiple stuck-open faults for M≤n. A hardware architecture is discussed generating this sequence, and for n=1 a built-in self-test (BIST) approach is presented that detects all combinations of multiple combinational and single stuck-open faults. The sequences are of minimum length, and can be produced either by software, by an external chip, or be a BIST-structure. Using the latter, the hardware overhead would be of the same magnitude as a conventional pseudorandom architecture.
Open Access
Generating pseudo-exhaustive vectors for external testing
(1990) Hellebrand, Sybille; Wunderlich, Hans-Joachim; Haberl, Oliver F.
Over the past years special chips for external tests have been successfully used for random pattern testing. The authors present a technique for combining the advantages of such a low-cost test with the advantages of pseudoexhaustive testing, which are enhanced fault coverage and simplified test pattern generation. To achieve this goal, two tasks are accomplished. First, an algorithm is developed for pseudoexhaustive test pattern generation, which ensures a feasible test length. Second, a chip design for applying these test patterns to a device under test is presented. The chip is programmed by the output of the proposed algorithm and controls the entire test. The technique is first applied to devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.
Open Access
Identifying resistive open defects in embedded cells under variations
(2023) Najafi-Haghi, Zahra Paria; Wunderlich, Hans-Joachim
Small Delay Faults (SDFs) due to weak defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is within the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its observability is restricted. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defective devices without a major impact on yield.
Open Access
Integrated tools for automatic design for testability
(1988) Schmid, Detlef; Wunderlich, Hans-Joachim; Feldbusch, Fridtjof; Hellebrand, Sybille; Holzinger, Jürgen; Kunzmann, Arno
An increasing part of the overall costs of custom and semicustom integrated circuits has to be spent for test purposes, and therefore the integration of test and design seems to be a key of cost reduction. At the University of Karlsruhe a program system is currently developed supporting the design of testable circuits. The program system under work essentially solves three tasks: 1.) Selection of an economical test strategy. 2.) Implementation of necessary circuit modifications in order to enhance testability, retaining the circuit function by construction. 3.) Generation of the test program.
Open Access
The integration of test and high level synthesis in a general design environment
(1986) Schmid, Detlef; Camposano, Raúl; Kunzmann, Arno; Rosenstiel, Wolfgang; Wunderlich, Hans-Joachim
This paper describes the integration of new tools for both test and synthesis of integrated circuits. The presented design system CADDY (Carlsruhe Digital Design System) automatically transforms a functional description into a circuit structure. Besides this logic synthesis the system also automatically integrates a complete or incomplete scan path. The software tool PROTEST (PRObabilistic TESTability analysis tool) determines the random testability of the combinational parts of synthesized circuits and suggests optimized input signal probabilities to minimize the necessary test length. To generate these test patterns on chip a specific test hardware is proposed.
Open Access
Maximizing the fault coverage in complex circuits by minimal number of signatures
(1991) Wunderlich, Hans-Joachim; Ströle, Albrecht P.
Methods to minimize the number of evaluated signatures without reducing the fault coverage are presented. This is possible because the signatures can influence one another during the test execution. For a fixed test schedule a minimal subset of signatures can be selected, and for a predetermined minimal subset of signatures the test schedule can be constructed such that the fault coverage is maximum. Both approaches result in significant hardware savings when a self-test is implemented.