Browsing by Author "Wunderlich, Hans-Joachim (Prof. Dr. rer. nat.)"

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Open Access
Efficient algorithms for fundamental statistical timing analysis problems in delay test applications of VLSI circuits
(2016) Wagner, Marcus; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat.)
Tremendous advances in semiconductor process technology are creating new challenges for the delay test of today’s digital VLSI circuits. The complexity of state-of-the-art manufacturing processes does not only lead to greater process variability, it also makes today's integrated circuits more prone to defects such as resistive shorts and opens. As a consequence, some of the manufactured circuits do not meet the timing requirements set by the design specification. These circuits must be identified by delay testing and sorted out to ensure the quality of shipped products. Due to the increasing process variability, key transistor and interconnect parameters must be modelled as random variables. These random variables capture the uncertainty caused by process variability, but also the impact of modelling errors and variations in the operating conditions of the circuits, such as the temperature or the supply voltage. The important consequence for delay testing is that a particular delay test detects a delay fault of fixed size in only a subset of all manufactured circuits, which inevitably leads to the shipment of defective products. Despite the fact that this problem is well understood, today's delay test generation methods are unable to consider the distortion of the delay test results, caused by process variability. To analyse and predict the effectiveness of delay tests in a population of circuits which are functionally identical but have varying timing properties, statistical timing analysis is necessary. Although the large runtime of statistical timing analysis is a well known problem, little progress has been made in the development of efficient statistical timing analysis algorithms for the variability-aware delay test generation and delay fault simulation. This dissertation proposes novel and efficient statistical timing analysis algorithms for the variability-aware delay test generation and delay fault simulation in presence of large delay variations. For the detection of path delay faults, a novel probabilistic sensitization analysis is presented which analyses the impact of process variations on the sensitization of the target paths. Furthermore, an efficient method for approximating the probability of detecting small delay faults is presented. Beyond that, efficient statistical SUM and MAX-operations are proposed, which provide the fundamental basis of block-based statistical timing analysis. The experiment results demonstrate the high efficiency of the proposed algorithms.
Open Access
Efficient location-based logic diagnosis of digital circuits
(2012) Holst, Stefan; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat.)
Logic diagnosis is the task of finding defects within a random logic circuit based on its faulty behavior. Fast and accurate algorithms for logic diagnosis are an integral part of modern chip development. Classic diagnosis algorithms were often based on fault models which contain a priori assumptions on the behavior of defects. In recent technologies, fault model based approaches become ineffective because defect mechanisms get more and more complex. So research has started on location-based diagnosis algorithms, which use more general fault models or no model at all and report defective substructures directly. The generality however may also have a negative effect on the accuracy of the diagnosis results. With the lack of a fault model, a diagnosis algorithm has less knowledge on possible or likely malfunctions of a circuit. This increases the search space dramatically and may even lead to defect candidates which are physically impossible. Reducing a priori assumptions while retaining sufficient knowledge on likely defect mechanisms is the key to effective logic diagnosis. This work introduces the Conditional Line Flip (CLF) calculus as a way to describe arbitrary defects in logic circuits. This generalized fault modeling approach is used to investigate the assumptions made by diagnostic fault models and diagnosis algorithms found in the literature. The second main contribution of this work is a location-based logic diagnosis algorithm called Partially Overlapping Impact couNTER (POINTER). It builds directly upon the CLF calculus, works independently of any specialized fault model and offers powerful heuristics for sorting defect candidates according to their likelihood in physical chips. The POINTER approach is extended and modified to account for the particular challenges of high precision diagnostics in a lab, during production, and in autonomous online diagnosis in the field. Experimental results on industrial designs confirm that, despite its generality and lack of application specific knowledge, POINTER performs much better than previous diagnosis approaches. In cases where very high response compaction ratios are used, POINTER even enables fault model independent diagnosis for the first time.
Open Access
In-field structural methods for end-to-end automotive digital diagnosis
(2014) Cook, Alejandro; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat.)
The automotive domain has strongly relied on recent advances in semiconductor technology in order to offer customers a huge amount of appealing features of overwhelming complexity. As traditional functional tests are no longer sufficient to fulfill automotive diagnostic requirements, the analysis of automotive semiconductor failures has become a major quality concern. Semiconductor structural test solutions are already key technologies for the successful manufacturing of any integrated circuit. However, these techniques place stringent constraints on the test application process, which cannot be easily enforced outside the manufacturing environment. The methods and algorithms in this dissertation enable the introduction of structural test and diagnostic solutions into the failure analysis process of the automotive industry.
Open Access
Scalable deterministic logic built-in self test
(2006) Gherman, Valentin; Wunderlich, Hans-Joachim (Prof. Dr. rer. nat.)
The core-based design style of integrated circuits (ICs) helps to manage the development challenges brought by the ever increasing complexity of integrated systems and the ever tighter time-to-market. Nevertheless, test-related problems are still far away from having a unitary and satisfactory solution, especially in the system on a chip (SOC) context. For the test of ICs two reference approaches are available: external testing and built-in selftest (BIST), out of which a variety of hybrid test strategies are obtained by test resource partitioning (TRP). The final goal is to provide advantageous tradeoffs of the test evaluation indicators like: test development and application cost, hardware overhead, fault coverage, etc. BIST offers support for in-field, on-line, burn-in and at-speed test that is indispensable for delay fault testing. Moreover, tradeoffs between fault coverage, hardware overhead and test length are possible. External testing is characterized by flexibility, reduced hardware overhead and high fault coverage for a given test length. Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines the advantages of deterministic external testing and pseudo-random logic BIST (LBIST). Unfortunately, previously proposed DLBIST methods are unsuited for large ICs, since computation time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this work, a novel procedure for the development of the so-called bit-flipping DLBIST scheme is proposed, which has nearly linear complexity in terms of both computation time and memory consumption. This new method is based on the use of Binary Decision Diagrams (BDDs). The efficiency of the employed algorithms is demonstrated for industrial designs containing up to 2M gates. The embedded test sequences obtained by mapping deterministic cubes to pseudo-random sequences are also evaluated with respect to the coverage of non-target defects, which are modeled with the help of resistive bridging faults. The experimental results prove that both deterministic cubes and pseudo-random sequences are useful for detecting non-target defects. Moreover, possible tradeoffs between test length, hardware overhead, fault coverage and nontarget defect coverage are analyzed. This work additionally presents the results of extending the bit-flipping DLBIST scheme such that it also supports the transition fault testing besides the stuck-at fault testing. Transition faults model defects which are responsible for the incorrect operation of the core under test (CUT) at the desired speed. The importance of these defects is continuously enhanced by the ever increasing clock rates and integration density of today s circuits. Experimental results obtained for large industrial benchmark designs are reported. No pure DLBIST approach for the test of delay faults in circuits with standard scan design has been published so far. In order to decrease the logic overhead of DLBIST, an innovative way of constructing efficient implementations for the involved Boolean functions (e.g. bit-flipping functions) is presented. A key feature of these functions is their incomplete specification which is based on large don t care sets (sets of input assignments for which it does not matter whether they are mapped to 0 or 1 ). Reduced ordered Binary Decision Diagrams (ROBDD) are used for representing and manipulating the involved functions and multi-level implementations are obtained based on the use of free BDDs (FBDD). Experimental results show that for all the considered functions, implementations are found with a significant reduction of the gate count as compared to a state-of-the-art multi-level synthesys tool (SIS [Sen92]) or to methods offered by a state-of-the-art BDD package. This performance is due to a reduction of the node count in the corresponding FBDDs and a decrease in the average number of gates needed to implement the FBDD nodes. The experimental results obtained for large industrial benchmark designs show that DLBIST may be well suited for use in special segments of IC development, like the ones dealing with security chips or hard cores.