Parallel-Analog/Digital-Umsetzer für Gigabaud-Applikationen

Abstract

Communication systems with digital signal processors (DSPs) rely on data converters as interface blocks between the analog and the digital domain. The channel data rates in these systems can be increased by choosing a higher symbol rate and/or a more complex modulation format. Both approaches motivate the design of data converters with high sample rates and/or high effective bit resolution. As the improvement of the converter linearity in terms of power efficiency is more difficult to realize, especially at high operation frequencies, current research on ultrahigh data-rate mm-wave communication systems (e.g., 100 Gbit/s wireless communication) focuses on increasing the symbol rate while keeping the modulation format simple (e.g., quadrature phase shift keying). These systems require data converters with nominal bit resolutions of around 4-8 bit and sample rates of more than 25 GS/s. In order to satisfy the future needs for high-speed data converters, new circuit topologies need to be investigated. This work presents the design of a 35.84-GS/s 4-bit analog-to-digital converter (ADC) from its idea to its first silicon implementation. The ADC is based on a single-core flash architecture that makes use of a special traveling-wave signal distribution. Contrary to classical approaches with a power-hungry and area-consuming front-end track-and-hold (T/H), no analog preprocessing is needed. The analog input and the clock signal are rather directly distributed over a pair of delay-matched transmission lines from one comparator to the next adjacent one. Due the spatial location of these components, both signals do not arrive at the same time at every comparator, but as they travel synchronously along the transmission lines, each comparator will always see the same input value at each sampling event. This work gives detailed insight into critical design aspects of this approach and new mathematical models to predict the impact of data-to-clock time skews onto the converter linearity. Furthermore, essential building components (e.g., linear amplifiers, encoder, etc.) and a real-time digital communication interface for multi-gigabit/s data transmission to external devices are presented. The ADC is implemented in a 130-nm SiGe BiCMOS technology from IHP (SG13G2) and exhibits a die area of 1.3 mm^2. For experimental tests, the ADC is wire-bonded on a specially designed radio frequency (RF) printed circuit board. At a sampling rate of 35.84 GS/s, the peak spurious-free dynamic range (SFDR) is 35.4 dBc and the peak signal-to-noise-and-distortion ratio (SNDR) is 24.6 dB (3.8 bit). The effective resolution bandwidth (ERBW) is 14.52 GHz and covers almost the complete first Nyquist frequency band. Up to input frequencies of 20 GHz, a SFDR of more than 26.7 dBc and a SNDR of more than 19.8 dB (3 bit) is achieved. Even at a sample rate of 40.32 GS/s, full Nyquist performance can be demonstrated (SNDR = 18.4 dB @20 GHz). The presented ADC improves the sample rate of current state-of-the-art single-core ADCs by 61% from 25 GS/s to 40 GS/s, making it not only the smallest, but also the fastest reported single-core implementation up to date.