Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-11780
|Title:||Switching characteristics of integrated GaN-on-Si half-bridge and driver circuits|
|Abstract:||This work examines particularities in the switching characteristics of gallium nitride (GaN) half-bridge and driver circuits, which arise from the integration on a common conductive silicon (Si) substrate, or from the operation of discrete devices on an electrically coupled Si substrate. The supposed advantages of monolithic integrated half-bridges and drivers are promising: The reduced parasitic interconnect inductance improves voltage-switching transitions. The Si carrier allows low-cost and large-scale fabrication. A single integrated IC simplifies the assembly compared to conventional multi-chip power modules. However, the operation of such monolithic GaN-on-Si power circuits also evokes substrate-related effects, especially at elevated operation voltages, which were previously not relevant for single low-side GaN HEMTs. On the one hand, deteriorating effects such as on-resistance increase by negative substrate biasing (back-gating) have to be considered. On the other hand, beneficial effects such as the possibility of decoupling of substrate capacitances can be exploited for reduction of switching energies and consequently increased efficiencies compared to conventional discrete GaN power transistors. Furthermore, even though the monolithic integration of a gate driver with a power transistor reduces the interconnect parasitics between the driver and the transistor, still external interconnects to decoupling capacitors are required. The monolithic integration of half-bridges and drivers thus does not fully eliminate parasitic gate-loop and power-loop inductance. Therefore, advanced assembly technologies such as PCB-embedding of GaN-based power integrated circuits should also be considered in combination with the monolithic circuit integration. First, this work provides a theoretical framework to calculate and compare the effect of substrate-capacitances on application-oriented half-bridge capacitances for different feasible substrate terminations of discrete and monolithic GaN-on-Si half-bridges. It is explained and verified how floating substrate terminations reduce the effective output capacitances. To harness the benefits of this reduced effective capacitances, an improved passive substrate biasing network for monolithic half-bridges is proposed and experimentally verified: The proposed operation scheme for monolithic half-bridges avoids negative back-gating in all operation points of a dc-dc converter and at the same time has reduced effective output capacitance compared to a discrete half-bridge. Experimental operation of a monolithic half-bridge with the proposed substrate biasing network shows increased efficiency compared to a discrete half-bridge and verifies the effectiveness of the proposed duty-cycle independent floating substrate biasing. Compared to a conventional discrete half-bridge with two substrate-to-source terminated transistors, this work's operation scheme for a monolithic half-bridge in a dc-dc converter with 200 V input voltage, 100 V output voltage, 1.5 A load current and 100 kHz switching frequency, reduced the switching energies by over 20%, and the total power loss in a dc-dc converter by over 10%. This efficiency improvement is the results of this work's beneficial combination of a (semi-)floating substrate which reduces the effective output capacitance, and the novel substrate biasing network which avoids negative back-gating during conduction phases by shifting the average substrate voltage towards higher values. Then, this work work analyzes high slew-rate voltage switching transitions and the effect of parasitic inductance in the power-loop on switch-node overshoot voltage. An equivalent circuit analysis is carried out, which takes the limited voltage slew-rate of a power transistor into account. In contrast to a simplified RLC-circuit analysis with a infinitely fast voltage excitation pulse, this work analytically provides insight into the dependency of switch-node overshoot voltage on the voltage transition time. Even though the power-loop is almost undamped due to the low on-resistance of the transistors, the analysis shows that local minima of overshoot as a function of switching time exist, and by selection of optimal switching times it is possible to minimize the overshoot without a significant reduction of switching speed. Furthermore, an advanced PCB-embedded packaging technology is combined with on-package gate and dc-link capacitors, which further reduces parasitic inductance of GaN half-bridges with integrated drivers. Finally, this work exposes that the substrate-to-source termination of a lateral GaN power transistor, which is typically realized on the packaging level, forms a third parasitic loop. In addition to the well-known parasitic gate-loop and power-loop inductance, this work analyzes the effects of this substrate-loop inductance. An analytical and experimental stability analysis is carried out. Countermeasures are proposed to avoid instabilities from the parasitic-substrate loop. A substrate damping circuit is proposed, which avoids instabilities by damping of the substrate-loop, without slowing down of the switching transition. The experimental and theoretical investigation and results of this work on the switching characteristic of GaN-on-Si half-bridges with drivers on conductive Si substrates contributes to unlock the benefits of GaN HEMTs and monolithic power circuit integration for compact, clean switching and highly efficient power electronics.|
|Appears in Collections:||05 Fakultät Informatik, Elektrotechnik und Informationstechnik|
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