Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-2844
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dc.contributor.authorAhmed, Silviade
dc.date.accessioned2012-05-15de
dc.date.accessioned2016-03-31T07:59:34Z-
dc.date.available2012-05-15de
dc.date.available2016-03-31T07:59:34Z-
dc.date.issued2011de
dc.identifier.other369340574de
dc.identifier.urihttp://nbn-resolving.de/urn:nbn:de:bsz:93-opus-74032de
dc.identifier.urihttp://elib.uni-stuttgart.de/handle/11682/2861-
dc.identifier.urihttp://dx.doi.org/10.18419/opus-2844-
dc.description.abstractThis thesis investigates the scope of parallelism of the lossless JPEG-LS encoder. The input is not taken to be the entire image anymore; instead it is streams of pixels from an image sensor in every clock cycle. So the data dependencies that already exist due to the context modelling process and the effect of incomplete image data were analyzed thoroughly here. Other approaches of parallelism in JPEG-LS (e.g. pipelined hardware or software implementations that modify the context update procedures) deviate from the standard defined by ISO/ITU. On the other hand, the proposed technique here is fully compatible to the standard. In this work, a unique pixel loading mechanism (i.e. in the form that the encoder expects them to be) was developed from the streams of pixel. Later in order to store the pixels of the same context that are yet to be processed, another unique buffering mechanism was developed. However the context distribution of individual pixel determines the maximum achievable parallelism and thus a fixed value is not guaranteed in any case. The thesis also presents a vhdl implementation of the proposed parallel JPEG-LS encoder. The target hardware for this design was an FPGA board (Virtex 5). The design was also compared with the sequential hardware implementation and other parallel implementation in terms of speed up mainly. However there were some obstacles that restricted the actual synthesis. Possible reasons behind them are discussed with further suggestions for future work.en
dc.language.isoende
dc.rightsinfo:eu-repo/semantics/openAccessde
dc.subject.ddc004de
dc.titleParallel hardware architecture for JPEG-LS based on domain decomposition using context setsen
dc.typemasterThesisde
ubs.fakultaetFakultät Informatik, Elektrotechnik und Informationstechnikde
ubs.institutInstitut für Parallele und Verteilte Systemede
ubs.opusid7403de
ubs.publikation.typAbschlussarbeit (Master)de
Appears in Collections:05 Fakultät Informatik, Elektrotechnik und Informationstechnik

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