Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits

Abstract

The negative-bias temperature instability (NBTI) is one of the dominant aging degradation mechanisms in today Very Large Scale Integration (VLSI) Integrated Circuits (IC). With the further decreasing of the transistor dimensions and reduction of supply voltage, the NBTI degradation may become a critical reliability threat. Nevertheless, most of the EDA tools lack in the ability to predict and analyse the impact of the NBTI. Other tools able to analyse the NBTI, are often on very low design level and requiring significant computational resources.

The purpose of this master work is to analyse the impact of the NBTI aging degradation in the combinational part of VLSI CMOS circuits. For that purpose, a gate-level NBTI simulation flow for estimating the degraded circuit performance parameters is proposed and implemented. The flow is NBTI model independent and tool independent. A particular implementation is made based on the Reaction-Diffusion NBTI model, and the tools: HotSpot 5.0, Candance Encounter, Synopsys Design Compiler, Synopsys Prime-Time. The results of the NBTI simulation are outputted in the format of statistical data of the gate delay degradation, the critical path delay degradation and length change, and the power consumption change. In addition, a heatmap visualizing the delay degradation is generated.

Finally, a set of simulations are performed on circuits from the ISCAS89 and NXP benchmark suits. The statistical data are presented, and the impact of the NBTI degradation is analysed.