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http://dx.doi.org/10.18419/opus-7902
Autor(en): | Ströle, Albrecht P. Wunderlich, Hans-Joachim |
Titel: | Configuring flip-flops to BIST registers |
Erscheinungsdatum: | 1994 |
Dokumentart: | Konferenzbeitrag |
Erschienen in: | Proceedings / International Test Conference 1994. Piscataway, NJ : IEEE Service Center, 1994. - ISBN 0-7803-2102-2, S. 939-948. URL http://dx.doi.org./ 10.1109/TEST.1994.528043 |
URI: | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-72967 http://elib.uni-stuttgart.de/handle/11682/7919 http://dx.doi.org/10.18419/opus-7902 |
Zusammenfassung: | Built-in self-test test registers must segment a circuit such that there exists a feasible test schedule. If a register transfer description is used for selecting the positions of test registers, the space for optimizations is small. In this paper, 1-bit test cells are inserted at gate level, and an initial test schedule is constructed. Based on the information of this schedule, test cells that can be controlled in the same way are assembled to test registers. Finally, a test schedule at RT level is constructed and a minimal set of test control signals is determined. The presented approach can reduce both BIST hardware overhead and test application time. It is applicable to control units and circuits produced by control oriented synthesis where an RT description is not available. Considerable gains can also be obtained if existing RT structures are reconfigured for self-testing in the described way. |
Enthalten in den Sammlungen: | 15 Fakultätsübergreifend / Sonstige Einrichtung |
Dateien zu dieser Ressource:
Datei | Beschreibung | Größe | Format | |
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wun7.pdf | 3,13 MB | Adobe PDF | Öffnen/Anzeigen |
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