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dc.contributor.authorStern, Olafde
dc.contributor.authorWunderlich, Hans-Joachimde
dc.date.accessioned2012-04-18de
dc.date.accessioned2016-03-31T11:44:37Z-
dc.date.available2012-04-18de
dc.date.available2016-03-31T11:44:37Z-
dc.date.issued1994de
dc.identifier.other369583035de
dc.identifier.urihttp://nbn-resolving.de/urn:nbn:de:bsz:93-opus-72944de
dc.identifier.urihttp://elib.uni-stuttgart.de/handle/11682/7929-
dc.identifier.urihttp://dx.doi.org/10.18419/opus-7912-
dc.description.abstractFor obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavior. In this paper, a method is presented for computing the occurrence probabilities of certain defects and the realistic fault coverage for test sets. The method is highly efficient as a pre-processing step is used for partitioning the layout and extracting the defects ranked in the order of their occurrence probabilities. The method was applied to a public domain library where defects causing a complex faulty behavior are possible. The occurrence probability of these faults was computed, and the defect coverage for different test sets was determined.en
dc.language.isoende
dc.rightsinfo:eu-repo/semantics/openAccessde
dc.subject.classificationCMOS , Fehlererkennung , Prüfprogrammde
dc.subject.ddc621.3de
dc.titleSimulation results of an efficient defect analysis procedureen
dc.typeconferenceObjectde
ubs.fakultaetFakultätsübergreifend / Sonstige Einrichtungde
ubs.institutSonstige Einrichtungde
ubs.opusid7294de
ubs.publikation.sourceProceedings / International Test Conference 1994. Piscataway, NJ : IEEE Service Center, 1994. - ISBN 0-7803-2102-2, S. 729-738. URL http://dx.doi.org./ 10.1109/TEST.1994.528019de
ubs.publikation.typKonferenzbeitragde
Enthalten in den Sammlungen:15 Fakultätsübergreifend / Sonstige Einrichtung

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