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http://dx.doi.org/10.18419/opus-7922
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DC Element | Wert | Sprache |
---|---|---|
dc.contributor.author | Ströle, Albrecht P. | de |
dc.contributor.author | Wunderlich, Hans-Joachim | de |
dc.date.accessioned | 2012-04-23 | de |
dc.date.accessioned | 2016-03-31T11:44:39Z | - |
dc.date.available | 2012-04-23 | de |
dc.date.available | 2016-03-31T11:44:39Z | - |
dc.date.issued | 1990 | de |
dc.identifier.other | 369846664 | de |
dc.identifier.uri | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73162 | de |
dc.identifier.uri | http://elib.uni-stuttgart.de/handle/11682/7939 | - |
dc.identifier.uri | http://dx.doi.org/10.18419/opus-7922 | - |
dc.description.abstract | The effects of error masking in a number of signature registers are analyzed. It is shown that a self-test can always be scheduled such that evaluating signatures only at the end of the complete test execution is sufficient. A method for computing the probability of a fault leading to at least one faulty signature in a set of self-test registers is presented. This method allows the computation of the fault coverage with respect to the complete test execution. A minimal subset of all self-test registers can be selected so that only the signatures of these self-test registers have to be evaluated and the fault coverage is almost not affected. The benefits of this approach are a smaller number of self-test registers in the scan path, a smaller number of signatures to be evaluated, a simplified test control unit, and hence a significant reduction in tie hardware required for built-in self-test structures. The proposed method is illustrated by an example and validated by simulation. | en |
dc.language.iso | en | de |
dc.rights | info:eu-repo/semantics/openAccess | de |
dc.subject.classification | Selbsttest , Integrierte Schaltung , Signaturanalyse | de |
dc.subject.ddc | 621.3 | de |
dc.title | Error masking in self-testable circuits | en |
dc.type | conferenceObject | de |
dc.date.updated | 2012-04-23 | de |
ubs.fakultaet | Fakultätsübergreifend / Sonstige Einrichtung | de |
ubs.institut | Sonstige Einrichtung | de |
ubs.opusid | 7316 | de |
ubs.publikation.source | Denburg, Donald (Hrsg.): The changing philosophy of test : proceedings. Piscataway, NJ : IEEE Computer Soc. Pr., 1990. - ISBN 0-8186-2064-1, S. 544-552. URL http://dx.doi.org./10.1109/TEST.1990.114066 | de |
ubs.publikation.typ | Konferenzbeitrag | de |
Enthalten in den Sammlungen: | 15 Fakultätsübergreifend / Sonstige Einrichtung |
Dateien zu dieser Ressource:
Datei | Beschreibung | Größe | Format | |
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wun23.pdf | 1,58 MB | Adobe PDF | Öffnen/Anzeigen |
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