Generating pseudo-exhaustive vectors for external testing

Abstract

Over the past years special chips for external tests have been successfully used for random pattern testing. The authors present a technique for combining the advantages of such a low-cost test with the advantages of pseudoexhaustive testing, which are enhanced fault coverage and simplified test pattern generation. To achieve this goal, two tasks are accomplished. First, an algorithm is developed for pseudoexhaustive test pattern generation, which ensures a feasible test length. Second, a chip design for applying these test patterns to a device under test is presented. The chip is programmed by the output of the proposed algorithm and controls the entire test. The technique is first applied to devices with a scan path and then extended to sequential circuits. A large number of benchmark circuits have been investigated, and the results are presented.