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http://dx.doi.org/10.18419/opus-7937
Autor(en): | Haberl, Oliver F. Wunderlich, Hans-Joachim |
Titel: | The synthesis of self-test control logic |
Erscheinungsdatum: | 1989 |
Dokumentart: | Konferenzbeitrag |
Erschienen in: | VLSI and computer peripherals : proceedings. Washington, DC : IEEE Computer Soc. Pr., 1989. - ISBN 0-8186-1940-6, S. 5/134-5/136. URL http://dx.doi.org./10.1109/CMPEUR.1989.93499 |
URI: | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73395 http://elib.uni-stuttgart.de/handle/11682/7954 http://dx.doi.org/10.18419/opus-7937 |
Zusammenfassung: | In recent years, many built-in self-test techniques have been proposed based on feedback shift-registers for pattern generation and signature analysis. But in general, these test-registers cannot test several modules of the chip concurrently, and they have to be controlled by external automatic test equipment. The authors propose a method to integrate additional test-control logic into the chip. On the basis of a register-transfer description of the circuit, the test control is derived, and a corresponding finite automation is synthesized. A hardware implementation is proposed, resulting in circuits where the entire self-test only consists in activating the test mode and clocking and evaluating the overall signature. |
Enthalten in den Sammlungen: | 15 Fakultätsübergreifend / Sonstige Einrichtung |
Dateien zu dieser Ressource:
Datei | Beschreibung | Größe | Format | |
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wun37.pdf | 3,06 MB | Adobe PDF | Öffnen/Anzeigen |
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