Synthesis of self-testable controllers

Abstract

The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test registers. Hence the additional delay imposed by the test circuitry is reduced, the fault coverage is increased, and in many cases the overall area is minimal too. The self-testable structure for a given finite state machine specification is derived from all appropriate reaiization of the machine. A theorem is proven that such realizations can be constructed by means of partition pairs. An algorithm to determine realizations is developed and benchmark experiments are presented to demonstrate the applicability of the presented approach.