Please use this identifier to cite or link to this item:
http://dx.doi.org/10.18419/opus-8196
| Authors: | Wang, Zhigong Berroth, Manfred Hurm, Volker Lang, Manfred Hofmann, Peter Hülsmann, Axel Köhler, Klaus Raynor, Brian Schneider, Joachim |
| Title: | 20 Gb/s monolithic integrated clock recovery and data decision |
| Issue Date: | 1994 |
| metadata.ubs.publikation.typ: | Konferenzbeitrag |
| metadata.ubs.publikation.source: | Twentieth European Solid-State Circuits : Ulm, Germany, September 20-22, 1994; proceedings. Gif-sur-Yvette : Editions Frontières, 1994. - ISBN 2-86332-160-9, S. 176-179 |
| URI: | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-92492 http://elib.uni-stuttgart.de/handle/11682/8213 http://dx.doi.org/10.18419/opus-8196 |
| Abstract: | An IC for 20 Gb/s clock recovery and data decision was realised using 0.3 m gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals have been obtained. The 2x2 mm 2 IC has a power consumption of about 0.5 W at -3 volt supply voltage. |
| Appears in Collections: | 15 Fakultätsübergreifend / Sonstige Einrichtung |
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