Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-8204
|Title:||7.5 Gb/s monolithically integrated clock recovery using PLL and 0.3 μM gate length quantum well HEMTs|
|metadata.ubs.publikation.source:||Proceedings / ESSCIRC '93 : Sevilla, Spain, September 22-24, 1993. Gif-sur-Yvette : Ed. Frontières, 1993. - ISBN 2-86335-134-X, S. 222-225|
|Abstract:||A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well high electron mobility transistors (QW-HEMTs) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO has been introduced. The VCO has a centre oscillating frequency of about 7.5 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at the bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at the supply voltage of -5 V.|
|Appears in Collections:||15 Fakultätsübergreifend / Sonstige Einrichtung|
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