Browsing by Author "Burghartz, Joachim N. (Prof. Dr.-Ing.)"

Now showing 1 - 3 of 3

Open Access
Ablenk-Systeme für die Multi-Elektronenstrahllithografie auf Basis CMOS-kompatibler Fertigungsprozesse
(2017) Jurisch, Michael; Burghartz, Joachim N. (Prof. Dr.-Ing.)
Open Access
Hybrid system-in-foil integration and interconnection technology based on adaptive layout technique
(2019) Alavi, Golzar; Burghartz, Joachim N. (Prof. Dr.-Ing.)
The Hybrid System-in-Foil (HySiF) including ultra-thin embedded silicon chips in polymer foil in combination with large area electronics, such as organic thin-film transistors (OTFTs), capacitive sensors, antennas, and strain gauges is a promising technological solution for the next generation of consumers in the field of flexible electronics. This work mainly contributes to developing the CMOS-compatible process flow to embed and interconnect ultra-thin silicon chips inside polymer foil in combination with other devices. The fine-pitch (10 µm) chip to foil interconnectivity is pursued by relocating the active pads on a silicon chip to the foil periphery, therefore, saving silicon area and costs and providing a far larger I/O count is possible. The Chip-Film Patch (CFP) concept is suitable for HySiF technology. However, limitations often exist due to restriction in processing methods and incompatibility of the material with an IC processing fabrication line. These issues and corresponding solutions are treated in this thesis. Besides optimization of the already published concept of two-polymer CFP and bringing that to fabrication level, key aspects of this dissertation are: - The process flow development of face-up low-stress CFP technology to avoid the coefficient of thermal expansion (CTE) mismatch between embedded silicon chips, deposited polymer layers, and silicon substrate carrier. - The fabrication process of the face-down CFP technology to minimize topography on top of the embedded chip, thus, reaching finer pitch and pad size. Embedding devices with different thickness and chip backside processing are other advantages of the face-down CFP technology. - The challenge of unwanted rotation and positioning offset after chip embedding on foil using an adaptive layout technique based on laser direct writer lithography. Using the adaptive layout technique, wafer level embedding and interconnecting of multiple silicon chips as a HySiF become possible. The overlay accuracy below 1 µm in x-axis and y-axis for any arbitrary position of the embedded chip is achieved. - The thermal behavior of power chips embedding in polymer foil and self-heating phenomenon and corresponding cooling methods, such as heat spreader on the chip’s backside. - The CMOS-compatible process flow to fabricate a rigid mm-wave patch antenna and flexible dipole antenna in polymer foil with antennas that are fabricated, measured, and high-frequency properties of the polymer packages are extracted.
Open Access
Short-channel organic thin-film transistors : fabrication, characterization, modeling and circuit demonstration
(2014) Zaki, Tarek; Burghartz, Joachim N. (Prof. Dr.-Ing.)
Plastic electronics based on organic thin-film transistors (OTFTs) pave the way for cheap, flexible and large-area products. Over the past few years, OTFTs have undergone remarkable progress in terms of reliability, Performance and scale of integration. This work takes advantage of high-Resolution Silicon stencil masks to build air-stable complementary OTFTs using a low-temperature fabrication process. Many factors contribute to the allure of this technology; the masks exhibit excellent stiffness and stability, thus allowing to pattern the OTFTs with submicrometer channel lengths and superb device uniformity. Furthermore, the OTFTs employ an ultra-thin gate dielectric that provides a sufficiently high capacitance of the order of 1 uF/cm^2 to enable the transistors to operate at voltages as low as 3 V. The critical challenges in this development are the subtle mechanisms that govern the properties of the aggressively-scaled OTFTs. These mechanisms, dictated by device physics, have to be described and implemented into circuit design tools to ensure adequate simulation accuracy. This is particularly beneficial to gain deeper insight into materials-related limitations. The primary objective of this work is to bridge the gap between device modeling and mixed-signal circuits by establishing an OTFT compact model, together with realizing the world-fastest organic digital-to-analog converter (DAC). A unified model that captures the essence in the static/dynamic behavior of the OTFTs is derived. Approaches to incorporate the implicit bias-dependent parasitic effects in the model are elucidated and accordingly a reliable fit to experimental data of OTFTs with different dimensions is obtained. It is demonstrated that the charge storage behavior in the intrinsic OTFTs agrees very well with Meyer's capacitance model. Moreover, the first comprehensive study of the frequency response of OTFTs using S-Parameter characterization is presented. In view of the low supply voltage and air stability, a record cutoff frequency of 3.7 MHz for a channel length of 0.6 um and a gate overlap of 5 um is accomplished. Finally, a 6-bit current-steering DAC, comprising as many as 129 OTFTs, is designed. The converter achieves a thousand-fold faster update rate (100 kS/s) than prior state of the art.