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http://dx.doi.org/10.18419/opus-2928
Autor(en): | Buntoro, David Prasetyo |
Titel: | Modeling of design-for-test infrastructure in complex systems-on-chips |
Erscheinungsdatum: | 2012 |
Dokumentart: | Abschlussarbeit (Master) |
URI: | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-78052 http://elib.uni-stuttgart.de/handle/11682/2945 http://dx.doi.org/10.18419/opus-2928 |
Zusammenfassung: | Every integrated circuit contains a piece of design-for-test (DFT) infra- structure in order to guarantee the chip quality after manufacture. The DFT resources are employed only once in the fab and are usually not available during regular system operation. In order to assess the hardware integrity of a chip over its complete life- cycle, it is promising to reuse the DFT infrastructure as part of system- level test. In this thesis, the provided system, a Tricore processor from Infineon, must be partitioned and modified in order to enable the autonomous structural test of every component of the system in the field without expensive external tester. |
Enthalten in den Sammlungen: | 05 Fakultät Informatik, Elektrotechnik und Informationstechnik |
Dateien zu dieser Ressource:
Datei | Beschreibung | Größe | Format | |
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MSTR_3304.pdf | 1,05 MB | Adobe PDF | Öffnen/Anzeigen |
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