Development of a graphical numerical accuracy debugger based on an FPGA computing system

Abstract

In scientific computing, the number of floating point operations are increasing along with the higher performance of computers, as well as the larger problem size. Due to the finite representation of real numbers in computers, the calculated results are rounded into the representative numbers, which results in round-off errors. The round-off errors might be propagated as the program runs longer and in the end leads to an unreliable result. Discrete Stochastic Arithmetic (DSA) provides a method to evaluate the accuracy of computed results and detect numerical instabilities during execution of the program. The DSA has been implemented on an FPGA-based hardware system. The FPGA-based hardware system has N parallel processing blocks so that it can run the same piece of code N times in parallel in different round-off error propagations, which is required by DSA. In this thesis, based on this hardware architecture, a graphical numerical accuracy debugger is developed. Using this graphical numerical accuracy debugger, the user can debug same piece of code in both PowerPC processors synchronously, without any modification to source codes. In order to implement the proposed debugging flow, a script has been written to substitute the original underlying debugging engine of SDK. Within the script, a series of functionalities are achieved: GDB input commands catching/forwarding, process calling, GDB output messages catching/forwarding etc. Moreover, with the substitution, it’s able to collect results from all processing blocks and then the number of significant bits can be calculated and presented to users.