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http://dx.doi.org/10.18419/opus-7900
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DC Element | Wert | Sprache |
---|---|---|
dc.contributor.author | Ströle, Albrecht P. | de |
dc.contributor.author | Wunderlich, Hans-Joachim | de |
dc.date.accessioned | 2012-04-17 | de |
dc.date.accessioned | 2016-03-31T11:44:35Z | - |
dc.date.available | 2012-04-17 | de |
dc.date.available | 2016-03-31T11:44:35Z | - |
dc.date.issued | 1991 | de |
dc.identifier.other | 369503465 | de |
dc.identifier.uri | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73123 | de |
dc.identifier.uri | http://elib.uni-stuttgart.de/handle/11682/7917 | - |
dc.identifier.uri | http://dx.doi.org/10.18419/opus-7900 | - |
dc.description.abstract | In self-testable circuits, additional hardware is incorporated for generating test patterns and evaluating test responses. A built-off test strategy is presented which moves the additional hardware to a programmable extra chip. This is a low-cost test strategy in three ways: (1) the use of random patterns eliminates the expensive test-pattern computation; (2) a microcomputer and an ASIC (application-specific IC) replace the expensive automatic test equipment; and (3) the design for testability overhead is minimized. The presented ASIC generates random patterns, applies them to a circuit under test, and evaluates the test responses by signature analysis. It contains a hardware structure that can produce weighted random patterns corresponding to multiple programmable distributions. These patterns give a high fault coverage and allow short test lengths. A wide range of circuits can be tested as the only requirement is a scan path and no other test structures have to be built in. | en |
dc.language.iso | en | de |
dc.rights | info:eu-repo/semantics/openAccess | de |
dc.subject.classification | Selbsttest , Prüfprogramm , Signaturanalyse | de |
dc.subject.ddc | 621.3 | de |
dc.title | TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control | en |
dc.type | article | de |
dc.date.updated | 2014-10-16 | de |
ubs.fakultaet | Fakultätsübergreifend / Sonstige Einrichtung | de |
ubs.institut | Sonstige Einrichtung | de |
ubs.opusid | 7312 | de |
ubs.publikation.source | IEEE journal of solid-state circuits 26 (1991), S. 1056-1063. URL http://dx.doi.org./10.1109/4.92026 | de |
ubs.publikation.typ | Zeitschriftenartikel | de |
Enthalten in den Sammlungen: | 15 Fakultätsübergreifend / Sonstige Einrichtung |
Dateien zu dieser Ressource:
Datei | Beschreibung | Größe | Format | |
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wun20.pdf | 1,73 MB | Adobe PDF | Öffnen/Anzeigen |
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