Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-7918
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dc.contributor.authorKunzmann, Arnode
dc.contributor.authorWunderlich, Hans-Joachimde
dc.date.accessioned2012-04-23de
dc.date.accessioned2016-03-31T11:44:38Z-
dc.date.available2012-04-23de
dc.date.available2016-03-31T11:44:38Z-
dc.date.issued1990de
dc.identifier.other369726715de
dc.identifier.urihttp://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73243de
dc.identifier.urihttp://elib.uni-stuttgart.de/handle/11682/7935-
dc.identifier.urihttp://dx.doi.org/10.18419/opus-7918-
dc.description.abstractThe scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.en
dc.language.isoende
dc.rightsinfo:eu-repo/semantics/openAccessde
dc.subject.classificationFlip-Flop , Prüfprogramm , Fehlererkennungde
dc.subject.ddc621.3de
dc.titleAn analytical approach to the partial scan problemen
dc.typearticlede
ubs.fakultaetFakultätsübergreifend / Sonstige Einrichtungde
ubs.institutSonstige Einrichtungde
ubs.opusid7324de
ubs.publikation.sourceJournal of electronic testing 1 (1990), S. 163-174. URL http://dx.doi.org./10.1007/BF00137392de
ubs.publikation.typZeitschriftenartikelde
Appears in Collections:15 Fakultätsübergreifend / Sonstige Einrichtung

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