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http://dx.doi.org/10.18419/opus-7920
Autor(en): | Eschermann, Bernhard Wunderlich, Hans-Joachim |
Titel: | Parallel self-test and the synthesis of control units |
Erscheinungsdatum: | 1991 |
Dokumentart: | Konferenzbeitrag |
Erschienen in: | Proceedings / ETC 91. Berlin : VDE-Verl., 1991 - ISBN 3-8007-1778-6, S. 73-82 |
URI: | http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-73143 http://elib.uni-stuttgart.de/handle/11682/7937 http://dx.doi.org/10.18419/opus-7920 |
Zusammenfassung: | Most self-test techniques are implemented with so-called multifunctional test registers at any specific time either used for pattern generation or for response analysis. In a parallel self-test, however, test registers are used for pattern generation and response analysis simultaneously. In this paper a novel circuit structure for controllers with parallel self-test is presented, which does not result in a loss of fault coverage. By using a dedicated synthesis procedure, which considers the self-test hardware while generating the circuit structure instead of adding it after the design is completed ("synthesis for testability"), the self-test overhead can be kept low. The structure also facilitates realistic dynamic tests. As an example to illustrate the approach, the IEEE boundary scan controller is used. |
Enthalten in den Sammlungen: | 15 Fakultätsübergreifend / Sonstige Einrichtung |
Dateien zu dieser Ressource:
Datei | Beschreibung | Größe | Format | |
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wun21.pdf | 2,16 MB | Adobe PDF | Öffnen/Anzeigen |
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