Please use this identifier to cite or link to this item: http://dx.doi.org/10.18419/opus-7940
|Title:||Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits|
|metadata.ubs.publikation.source:||Digest of papers / the Eighteenth International Symposium on Fault-Tolerant Computing, FTCS-18, June 27-30, 1988, Keio Plaza Hotel, Tokyo. Piscataway, NJ : IEEE Service Center, 1988. - ISBN 0-8186-0867-6, S. 36-41. URL http://dx.doi.org./10.1109/FTCS.1988.5294|
|Abstract:||A method based on linear feedback shift registers over finite fields is presented to generate for a natural number n a pattern sequence with minimal length detecting each m-multiple stuck-open faults for M≤n. A hardware architecture is discussed generating this sequence, and for n=1 a built-in self-test (BIST) approach is presented that detects all combinations of multiple combinational and single stuck-open faults. The sequences are of minimum length, and can be produced either by software, by an external chip, or be a BIST-structure. Using the latter, the hardware overhead would be of the same magnitude as a conventional pseudorandom architecture.|
|Appears in Collections:||15 Fakultätsübergreifend / Sonstige Einrichtung|
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