Please use this identifier to cite or link to this item:
Authors: Berroth, Manfred
Hurm, Volker
Nowotny, Ulrich
Hülsmann, Axel
Kaufel, Gudrun
Köhler, Klaus
Raynor, Brian
Schneider, Joachim
Title: A 2.5 ns 8 x 8-b parallel multiplier using 0.5 μm GaAs/GaAlAs heterostructure field effect transistors
Issue Date: 1991 Zeitschriftenartikel Microelectronic engineering 15 (1991), S. 327-330. URL
Abstract: To increase performance of GaAs LSI digital circuits, a 0.5 μm recessed gate process has been developed and utilized for an 8x8-b parallel multiplier. The chip contains about 3000 heterostructure field effect transistors and has a power consumption of 1.5 W. The best results of the maximum multiplication time measured were below 2.5 nsec.
Appears in Collections:15 Fakultätsübergreifend / Sonstige Einrichtung

Files in This Item:
File Description SizeFormat 
ber16.pdf477,97 kBAdobe PDFView/Open

Items in OPUS are protected by copyright, with all rights reserved, unless otherwise indicated.